Semiconductor device and method for manufacturing the same

ABSTRACT

A highly reliable semiconductor device is provided. The semiconductor device includes a first barrier insulating film; a first gate electrode thereover; a first gate insulating film thereover; an oxide semiconductor film thereover; source and drain electrodes over the oxide semiconductor film; a second gate insulating film over the oxide semiconductor film; a second gate electrode over the second gate insulating film; a second barrier insulating film that covers the oxide semiconductor film, the source and the drain electrodes, and the second gate electrode, and is in contact with side surfaces of the oxide semiconductor film and the source and drain electrodes; and a third barrier insulating film thereover. The first to third barrier insulating films are less likely to transmit hydrogen, water, and oxygen than the first and second gate insulating films. The third barrier insulating film is thinner than the second barrier insulating film. The source and drain electrodes each includes a conductive oxide film in contact with the oxide semiconductor film. The conductive oxide film has more oxygen vacancies than the oxide semiconductor film.

BACKGROUND OF THE INVENTION 1. Field of the Invention

One embodiment of the present invention relates to a semiconductor device and a method for manufacturing the semiconductor device.

Note that one embodiment of the present invention is not limited to the above technical field. One embodiment of the invention disclosed in this specification and the like relates to an object, a method, or a manufacturing method. In addition, one embodiment of the present invention relates to a process, a machine, manufacture, or a composition of matter.

In this specification and the like, a semiconductor device generally means a device that can function by utilizing semiconductor characteristics. A display device (e.g., a liquid crystal display device or a light-emitting display device), a projection device, a lighting device, an electro-optical device, a power storage device, a memory device, a semiconductor circuit, an imaging device, an electronic device, and the like may include a semiconductor device.

2. Description of the Related Art

A technique in which a transistor is formed using a semiconductor thin film has been attracting attention. Such a transistor is applied to a wide range of electronic devices such as an integrated circuit (IC) and an image display device (also simply referred to as a display device). A silicon-based semiconductor material is widely known as a material for a semiconductor thin film applicable to a transistor. As another material, an oxide semiconductor has been attracting attention.

For example, a technique in which a display device is formed using a transistor including an oxide semiconductor (a zinc oxide or an In—Ga—Zn-based oxide) as an active layer is disclosed (see Patent Documents 1 and 2).

Moreover, in recent years, a technique in which an integrated circuit of a memory device is formed using a transistor including an oxide semiconductor has been disclosed (see Patent Document 3). In addition, not only the memory device but also an arithmetic device or other devices have been formed using a transistor including an oxide semiconductor.

However, it is known that a transistor including an oxide semiconductor as an active layer has a problem in that the electrical characteristics are easily changed by impurities and oxygen vacancies in the oxide semiconductor and thus the reliability is low. For example, the threshold voltage of the transistor is changed in some cases after a bias temperature stress test (BT test).

REFERENCE Patent Document

-   [Patent Document 1] Japanese Published Patent Application No.     2007-123861 -   [Patent Document 2] Japanese Published Patent Application No.     2007-096055 -   [Patent Document 3] Japanese Published Patent Application No.     2011-119674

SUMMARY OF THE INVENTION

An object of one embodiment of the present invention is to provide a semiconductor device having favorable reliability. Another object of one embodiment of the present invention is to provide a semiconductor device including an oxide semiconductor in which the concentration of impurities is reduced. Another object of one embodiment of the present invention is to provide a semiconductor device including an oxide semiconductor in which oxygen vacancies are reduced.

Another object of one embodiment of the present invention is to provide a semiconductor device having favorable electrical characteristics. Another object of one embodiment of the present invention is to provide a semiconductor device with low power consumption. Another object of one embodiment of the present invention is to provide a semiconductor device that can be miniaturized or highly integrated. Another object of one embodiment of the present invention is to provide a semiconductor device that can be manufactured with high productivity.

Note that the descriptions of these objects do not disturb the existence of other objects. In one embodiment of the present invention, there is no need to achieve all the objects. Other objects are apparent from and can be derived from the description of the specification, the drawings, the claims, and the like.

One embodiment of the present invention achieves reduction of oxygen vacancies in an oxide semiconductor by supplying excess oxygen to the oxide semiconductor from an oxide insulator in the vicinity of the oxide semiconductor.

Moreover, in order to prevent impurities such as water or hydrogen from entering an oxide semiconductor from an oxide insulator and the like in the vicinity of the oxide semiconductor, the oxide insulator and the like are dehydrated and dehydrogenated by heat treatment or the like. Furthermore, in order to prevent impurities such as water or hydrogen from entering the dehydrated and dehydrogenated oxide insulator and the like from the outside, an insulator having a barrier property against impurities such as water or hydrogen is formed to cover the oxide insulator and the oxide semiconductor.

Furthermore, the insulator having a barrier property against impurities such as water or hydrogen is made less likely to transmit oxygen. Accordingly, oxygen is prevented from diffusing outward and is effectively supplied to the oxide semiconductor and the oxide insulator in the vicinity thereof.

In another embodiment of the present invention, a conductor functioning as a source electrode and a drain electrode has a stacked-layer structure. A conductive oxide is used for layers of the source and drain electrodes that are in contact with an oxide semiconductor layer. With such a structure, impurities such as water or hydrogen in or in the vicinity of the oxide semiconductor layer can be gettered by the conductive oxide.

In such a manner, the concentration of impurities such as water or hydrogen contained in the oxide semiconductor and the oxide insulator in the vicinity thereof is reduced, and oxygen vacancies in the oxide semiconductor are reduced.

(1) One embodiment of the present invention is a semiconductor device including a first barrier insulating film; a first gate electrode over the first barrier insulating film; a first gate insulating film over the first gate electrode; an oxide semiconductor film over the first gate insulating film; a source electrode and a drain electrode that are apart from each other over the oxide semiconductor film; a second gate insulating film over the oxide semiconductor film, the source electrode, and the drain electrode; a second gate electrode which is over the second gate insulating film and at least part of which overlaps with a region between the source electrode and the drain electrode; a second barrier insulating film that covers the oxide semiconductor film, the source electrode, the drain electrode, the second gate electrode, and the second gate insulating film, and is in contact with side surfaces of the oxide semiconductor film, the source electrode, and the drain electrode and the top surface of the first gate insulating film; and a third barrier insulating film over the second barrier insulating film. The first barrier insulating film, the second barrier insulating film, and the third barrier insulating film are less likely to transmit hydrogen, water, and oxygen than the first gate insulating film and the second gate insulating film. The third barrier insulating film has a smaller thickness than the second barrier insulating film. The source electrode and the drain electrode have a stacked-layer structure. Layers of the source and drain electrodes that are in contact with the oxide semiconductor film each comprise a conductive oxide film. The conductive oxide film has a larger number of oxygen vacancies than the oxide semiconductor film.

(2) Another embodiment of the present invention is a semiconductor device including a first insulator; a second insulator over the first insulator; a first conductor over the second insulator; a third insulator over the first conductor; a first oxide over the third insulator; a second oxide over the first oxide; a first conductive oxide and a second conductive oxide that are apart from each other over the second oxide; a second conductor over the first conductive oxide; a third conductor over the second conductive oxide; a third oxide that is over the second oxide, the first conductive oxide, the second conductive oxide, the second conductor, and the third conductor and is in contact with the top surface and a side surface of the second oxide, a side surface of the first oxide, and the top surface of the third insulator; a fourth insulator over the third oxide; a fourth conductor positioned over the fourth insulator so that at least part of the fourth conductor overlaps with a region between the second conductor and the third conductor; a fifth insulator provided in contact with a side surface of the first conductive oxide, a side surface of the second conductive oxide, the side surface of the second oxide, and the top surface of the third insulator so as to cover the first to third oxides, the first conductive oxide, the second conductive oxide, the second to fourth conductors, and the fourth insulator; and a sixth insulator over the fifth insulator. The first, second, fifth, and sixth insulators are less likely to transmit hydrogen, water, and oxygen than the third and fourth insulators. The first insulator has a smaller thickness than the second insulator, and the sixth insulator has a smaller thickness than the fifth insulator. The first conductive oxide and the second conductive oxide each have a larger number of oxygen vacancies than the second oxide.

In the embodiment (2), the semiconductor device preferably further includes a seventh insulator provided in contact with the top surface of the fourth conductor. The seventh insulator is preferably less likely to transmit oxygen than the third and fourth insulators.

It is preferable that the semiconductor device of the embodiment (2) further include an eighth insulator in contact with the top surface of the second conductor; and a ninth insulator in contact with the top surface of the third conductor, and the eighth insulator and the ninth insulator be less likely to transmit oxygen than the third insulator and the fourth insulator. Furthermore, each of the eighth insulator and the ninth insulator preferably contains oxygen and aluminum.

The semiconductor device of the embodiment (2) further includes a tenth insulator over the sixth insulator, an eleventh insulator over the tenth insulator, and a twelfth insulator over the eleventh insulator. The third, fifth, sixth, and tenth insulators have an opening reaching the second insulator and the eleventh insulator is in contact with the top surface of the second insulator through the opening. The opening is provided so as to surround an external side of the second oxide. The eleventh insulator and the twelfth insulator are less likely to transmit hydrogen, water, and oxygen than the tenth insulator. The twelfth insulator preferably has a smaller thickness than the eleventh insulator.

In the embodiment (2), each of the first conductive oxide and the second conductive oxide preferably contains indium. In the embodiment (2), the density of indium contained in the first conductive oxide and the second conductive oxide is preferably higher than that of indium contained in the second oxide. In the embodiment (2), each of the first conductive oxide and the second conductive oxide preferably contains zinc. In the embodiment (2), each of the first conductive oxide and the second conductive oxide preferably contains tin and silicon.

In the embodiment (2), the first to third oxides preferably contain In, M (M is Al, Ga, Y, or Sn), and Zn. Moreover, the third and fourth insulators preferably contain oxygen and silicon. Furthermore, the first, second, fifth, and sixth insulators preferably contain oxygen and aluminum.

According to one embodiment of the present invention, a semiconductor device having favorable reliability can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device including an oxide semiconductor in which the concentration of impurities can be reduced can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device including an oxide semiconductor in which oxygen vacancies are reduced can be provided.

Alternatively, according to one embodiment of the present invention, a semiconductor device having favorable electrical characteristics can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device with low power consumption can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device that can be miniaturized or highly integrated can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device that can be manufactured with high productivity can be provided.

Note that the descriptions of these effects do not disturb the existence of other effects. In one embodiment of the present invention, there is no need to have all the effects. Other effects are apparent from and can be derived from the description of the specification, the drawings, the claims, and the like.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1A to 1E are a top view and cross-sectional views of a semiconductor device of one embodiment of the present invention.

FIGS. 2A to 2E illustrate a method for manufacturing a transistor of one embodiment of the present invention.

FIGS. 3A to 3E illustrate a method for manufacturing a transistor of one embodiment of the present invention.

FIGS. 4A to 4E illustrate a method for manufacturing a transistor of one embodiment of the present invention.

FIGS. 5A to 5E illustrate a method for manufacturing a transistor of one embodiment of the present invention.

FIGS. 6A to 6E illustrate a method for manufacturing a transistor of one embodiment of the present invention.

FIGS. 7A to 7E illustrate a method for manufacturing a transistor of one embodiment of the present invention.

FIGS. 8A to 8E illustrate a method for manufacturing a transistor of one embodiment of the present invention.

FIGS. 9A to 9E illustrate a method for manufacturing a transistor of one embodiment of the present invention.

FIGS. 10A to 10E illustrate a method for manufacturing a transistor of one embodiment of the present invention.

FIGS. 11A to 11E illustrate a method for manufacturing a transistor of one embodiment of the present invention.

FIGS. 12A to 12E illustrate a method for manufacturing a transistor of one embodiment of the present invention.

FIGS. 13A to 13E illustrate a method for manufacturing a transistor of one embodiment of the present invention.

FIGS. 14A to 14E illustrate a method for manufacturing a transistor of one embodiment of the present invention.

FIGS. 15A to 15E illustrate a method for manufacturing a transistor of one embodiment of the present invention.

FIGS. 16A to 16E illustrate a method for manufacturing a transistor of one embodiment of the present invention.

FIGS. 17A to 17E illustrate a method for manufacturing a transistor of one embodiment of the present invention.

FIGS. 18A to 18E illustrate a method for manufacturing a transistor of one embodiment of the present invention.

FIGS. 19A to 19E illustrate a method for manufacturing a transistor of one embodiment of the present invention.

FIGS. 20A to 20E illustrate a method for manufacturing a transistor of one embodiment of the present invention.

FIGS. 21A to 21E illustrate a method for manufacturing a transistor of one embodiment of the present invention.

FIG. 22 is a flowchart showing a method for manufacturing a semiconductor device of one embodiment of the present invention.

FIG. 23 is a flowchart showing a method for manufacturing a semiconductor device of one embodiment of the present invention.

FIG. 24 is an enlarged view of part of the view illustrating a method for manufacturing a transistor of one embodiment of the present invention.

FIGS. 25A to 25C each illustrate an atomic ratio range of an oxide semiconductor of one embodiment of the present invention.

FIGS. 26A to 26C are band diagrams of stacked-layer structures of oxide semiconductors.

FIGS. 27A to 27E are a top view and cross-sectional views of a semiconductor device of one embodiment of the present invention.

FIG. 28 is a cross-sectional view of a semiconductor device of one embodiment of the present invention.

FIG. 29 is a cross-sectional view of a semiconductor device of one embodiment of the present invention.

FIG. 30 is a cross-sectional view of a semiconductor device of one embodiment of the present invention.

FIGS. 31A and 31B show results of SSDP-SIMS analysis of Example of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

Embodiments are described in detail with reference to the drawings. Note that the present invention is not limited to the following description, and it is easily understood by those skilled in the art that various changes and modifications can be made without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited to the description in the following embodiments. Note that in the structures of the invention described below, the same portions or portions having similar functions are denoted by the same reference numerals in different drawings, and description of such portions is not repeated in some cases.

The position, size, range, and the like of each component illustrated in the drawings and the like are not accurately represented in some cases to facilitate understanding of the invention. Therefore, the disclosed invention is not necessarily limited to the position, size, range, and the like disclosed in the drawings and the like. For example, in the actual manufacturing process, a layer, a resist mask, or the like might be unintentionally reduced in size by treatment such as etching, which is not illustrated in some cases for easy understanding.

Especially in a top view (also referred to as a “plan view”), a perspective view, or the like, some components might not be illustrated for easy understanding of the invention. In addition, some hidden lines and the like might not be shown.

Ordinal numbers such as “first” and “second” in this specification and the like are used in order to avoid confusion among components and do not denote the priority or the order such as the order of steps or the stacking order. A term without an ordinal number in this specification and the like might be provided with an ordinal number in a claim in order to avoid confusion among components. A term with an ordinal number in this specification and the like might be provided with a different ordinal number in a claim. A term with an ordinal number in this specification and the like might not be provided with an ordinal number in a claim and the like.

In addition, in this specification and the like, a term such as an “electrode” or a “wiring” does not limit the function of a component. For example, an “electrode” is used as part of a “wiring” in some cases, and vice versa. Further, the term “electrode” or “wiring” can also mean a combination of a plurality of “electrodes” and “wirings” formed in an integrated manner.

Note that the term “over” or “under” in this specification and the like does not necessarily mean that a component is placed “directly above and in contact with” or “directly below and in contact with” another component. For example, the expression “electrode B over insulating layer A” does not necessarily mean that the electrode B is on and in direct contact with the insulating layer A and can mean the case where another component is provided between the insulating layer A and the electrode B.

Furthermore, functions of a source and a drain might be switched depending on operation conditions, e.g., when a transistor having a different polarity is employed or the direction of current flow is changed in circuit operation. Therefore, it is difficult to define which is the source (or the drain). Thus, the terms “source” and “drain” can be used to denote the drain and the source, respectively, in this specification.

Note that the channel length refers to, for example, a distance between a source (source region or source electrode) and a drain (drain region or drain electrode) in a region where a semiconductor (or a portion where a current flows in a semiconductor when a transistor is on) and a gate electrode overlap with each other or a region where a channel is formed in a top view of the transistor. In one transistor, channel lengths in all regions are not necessarily the same. In other words, the channel length of one transistor is not limited to one value in some cases. Therefore, in this specification, the channel length is any one of values, the maximum value, the minimum value, or the average value, in a region where a channel is formed.

The channel width refers to, for example, the length of a portion where a source and a drain face each other in a region where a semiconductor (or a portion where a current flows in a semiconductor when a transistor is on) and a gate electrode overlap with each other or a region where a channel is formed. In one transistor, channel widths in all regions are not necessarily the same. In other words, the channel width of one transistor is not limited to one value in some cases. Therefore, in this specification, the channel width is any one of values, the maximum value, the minimum value, or the average value, in a region where a channel is formed.

Note that depending on transistor structures, a channel width in a region where a channel is actually formed (hereinafter, referred to as an “effective channel width”) is different from a channel width shown in a top view of a transistor (hereinafter, referred to as an “apparent channel width”) in some cases. For example, in a transistor having a gate electrode covering side surfaces of a semiconductor, an effective channel width is greater than an apparent channel width, and its influence cannot be ignored in some cases. For example, in a miniaturized transistor having a gate electrode covering side surfaces of a semiconductor, the proportion of a channel formation region formed in the side surfaces of the semiconductor is increased in some cases. In that case, an effective channel width is greater than an apparent channel width.

In such a case, an effective channel width is difficult to measure in some cases. For example, estimation of an effective channel width from a design value requires an assumption that the shape of a semiconductor is known. Therefore, in the case where the shape of a semiconductor is not known accurately, it is difficult to measure an effective channel width accurately.

Therefore, in this specification, an apparent channel width is referred to as a “surrounded channel width (SCW)” in some cases. Furthermore, in this specification, in the case where the term “channel width” is simply used, it may denote a surrounded channel width or an apparent channel width. Alternatively, in this specification, in the case where the term “channel width” is simply used, it may denote an effective channel width in some cases. Note that the values of a channel length, a channel width, an effective channel width, an apparent channel width, a surrounded channel width, and the like can be determined by analyzing a cross-sectional TEM image and the like.

Note that in the case where field-effect mobility, a current value per channel width, and the like of a transistor are obtained by calculation, a surrounded channel width may be used for the calculation. In that case, the values may be different from those calculated using an effective channel width in some cases.

Note that impurities in a semiconductor refer to, for example, elements other than the main components of the semiconductor. For example, an element with a concentration of lower than 0.1 atomic % can be regarded as an impurity. When an impurity is contained, the density of states (DOS) in a semiconductor may be increased, the carrier mobility may be decreased, or the crystallinity may be decreased. In the case where the semiconductor is an oxide semiconductor, examples of an impurity that changes characteristics of the semiconductor include Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, and transition metals other than the main components of the oxide semiconductor; there are hydrogen, lithium, sodium, silicon, boron, phosphorus, carbon, and nitrogen, for example. In the case of an oxide semiconductor, water also serves as an impurity in some cases. In the case of an oxide semiconductor, oxygen vacancies may be formed by entry of impurities. In the case where the semiconductor is silicon, examples of an impurity that changes characteristics of the semiconductor include oxygen, Group 1 elements except hydrogen, Group 2 elements, Group 13 elements, and Group 15 elements.

In this specification, the term “parallel” indicates that the angle formed between two straight lines is greater than or equal to −10° and less than or equal to 10°, and accordingly also includes the case where the angle is greater than or equal to −5° and less than or equal to 5°. In addition, the term “substantially parallel” indicates that the angle formed between two straight lines is greater than or equal to −30° and less than or equal to 30°. In addition, the term “perpendicular” or “orthogonal” indicates that the angle formed between two straight lines is greater than or equal to 80° and less than or equal to 100°, and accordingly also includes the case where the angle is greater than or equal to 85° and less than or equal to 95°. In addition, the term “substantially perpendicular” indicates that the angle formed between two straight lines is greater than or equal to 60° and less than or equal to 120°.

In this specification and the like, the terms “identical”, “the same”, “equal”, “uniform”, and the like (including synonyms thereof) used in describing calculation values and actual measurement values allow for a margin of error of ±20% unless otherwise specified.

In this specification and the like, in the case where an etching step (removal step) is performed after a resist mask is formed by a photolithography method, the resist mask is removed after the etching step, unless otherwise specified.

Note that the terms “film” and “layer” can be interchanged with each other depending on the case or circumstances. For example, the term “conductive layer” can be changed into the term “conductive film” in some cases. Furthermore, the term “insulating film” can be changed into the term “insulating layer” in some cases. In addition, in this embodiment and the like, the term “insulator” can be replaced with the term “insulating film” or “insulating layer”. The term “conductor” can be replaced with the term “conductive film” or “conductive layer”. The term “semiconductor” can be replaced with the term “semiconductor film” or “semiconductor layer”. The term “oxide” can be replaced with the term “oxide film”.

Furthermore, unless otherwise specified, a transistor described in this specification and the like is an enhancement-type (normally-off type) field-effect transistor. Unless otherwise specified, a transistor described in this specification and the like refers to an n-channel transistor. Thus, unless otherwise specified, the threshold voltage (also referred to as “V_(th)”) is higher than 0 V.

Embodiment 1

In this embodiment, a semiconductor device including a transistor having favorable reliability and a method for manufacturing the semiconductor device are described with reference to FIGS. 1A to 1E through FIGS. 27A to 27E. A transistor provided in a semiconductor device of this embodiment includes an oxide semiconductor in an active layer. The reliability of the transistor provided in the semiconductor device can be improved by reducing the concentration of impurities such as water or hydrogen in the oxide semiconductor and reducing oxygen vacancies by supplying excess oxygen.

<Structure Example of Semiconductor Device 1000>

FIGS. 1A to 1E are a top view and cross-sectional views of a semiconductor device 1000. The semiconductor device 1000 includes a transistor 200 and a transistor 400. The transistors 200 and 400 formed over a substrate (not illustrated) have different structures. For example, the transistor 400 may have a smaller drain current than the transistor 200 when a back gate voltage and a top gate voltage are each 0 V (this drain current is hereinafter referred to as I_(CUT)). The transistor 400 is a switching element capable of controlling the potential of a back gate of the transistor 200. Therefore, a charge at a node connected to the back gate of the transistor 200 can be prevented from being lost by making the node have a desired potential and then turning off the transistor 400.

Here, FIG. 1A is a top view of the semiconductor device 1000. FIG. 1B is a cross-sectional view of the transistor 200 and the transistor 400 in the channel length direction, which is taken along dashed-dotted line L1-L2 in FIG. 1A. FIG. 1C is a cross-sectional view of the transistor 200 in the channel width direction, which is taken along dashed-dotted line W1-W2 in FIG. 1A. FIG. 1D is a cross-sectional view of the transistor 200 in the channel width direction, which is taken along dashed-dotted line W3-W4 in FIG. 1A. FIG. 1E is a cross-sectional view of the transistor 400 in the channel width direction, which is taken along dashed-dotted line W5-W6 in FIG. 1A.

Hereinafter, the structure of each of the transistors 200 and 400 is described with reference to FIGS. 1A to 1E. Note that detailed description of the materials of each of the transistors 200 and 400 is made in <Materials>.

[Transistor 200]

As illustrated in FIGS. 1A to 1D, the transistor 200 includes an insulator 212 over an insulator 210; an insulator 214 over the insulator 212; a conductor 205 (a conductor 205 a and a conductor 205 b) over the insulator 214; an insulator 220, an insulator 222, and an insulator 224 over the conductor 205; an oxide 230 (an oxide 230 a, an oxide 230 b, and an oxide 230 c) over the insulator 224; a conductive oxide 241 a and a conductive oxide 241 b (hereinafter, the conductive oxides 241 a and 241 b may be collectively referred to as a conductive oxide 241) over the oxide 230 b; a conductor 240 a and a conductor 240 b (hereinafter, the conductors 240 a and 240 b may be collectively referred to as a conductor 240) over the conductive oxide 241; a layer 245 a and a layer 245 b (hereinafter, the layers 245 a and 245 b may be collectively referred to as a layer 245) over the conductor 240; an insulator 250 over the oxide 230 c; a conductor 260 (a conductor 260 a, a conductor 260 b, and a conductor 260 c) over the insulator 250; a layer 270 over the conductor 260 c; an insulator 272 over the layer 270; and an insulator 274 over the insulator 272.

Each of the insulators 212 and 214 can function as a barrier insulating film for preventing impurities such as water or hydrogen from entering the transistor 200 and the like from a layer below the insulators 212 and 214. The insulators 212 and 214 are each preferably formed using an insulating material that is less likely to transmit impurities such as water or hydrogen, and for example, are preferably formed using aluminum oxide or the like. Accordingly, diffusion of impurities such as water or hydrogen from a layer under the insulator 210 into a layer over the insulators 212 and 214 can be inhibited. Note that it is preferable that at least one of impurities such as a hydrogen atom, a hydrogen molecule, a water molecule, a nitrogen atom, a nitrogen molecule, a nitrogen oxide molecule (e.g., N₂O, NO, and NO₂), and a copper atom be less likely to penetrate the insulators 212 and 214. Furthermore, hereinafter, the same applies to the description of an insulating material that is less likely to transmit impurities.

The insulator 212 is preferably formed using an atomic layer deposition (ALD) method, for example. Accordingly, the insulator 212 can have favorable coverage, and formation of cracks, pin holes, and the like in the insulator 212 can be prevented. In addition, the insulator 214 is preferably formed using a sputtering method, for example. Accordingly, the insulator 214 can be formed at a higher deposition rate than the insulator 212 and can have a larger thickness with high productivity than the insulator 212. Such a stack of the insulators 212 and 214 can have a higher barrier property against impurities such as water or hydrogen. Note that the insulator 212 may be provided over the insulator 214. Furthermore, when the insulator 214 has a sufficient barrier property against impurities, the insulator 212 is not necessarily provided.

Furthermore, for the insulators 212 and 214, an insulating material that is less likely to transmit oxygen (e.g., an oxygen atom or an oxygen molecule) is preferably used. With this material, oxygen contained in the insulator 224 or the like can be inhibited from diffusing into lower layers. Thus, oxygen can be supplied to the oxide 230 b effectively.

An opening penetrating the insulator 210, the insulator 212, and the insulator 214 is formed. In addition, a plurality of openings are formed in an insulator 216. At least one of the openings is formed to overlap with the position of the opening formed in the insulators 210, 212, and 214. The diameter of the opening formed in the insulator 216 is larger than that of the opening formed in the insulators 210, 212, and 214. In addition, the other openings in the insulator 216 reach the top surface of the insulator 214, and the top surface of the insulator 214 is depressed at positions of the openings in the insulator 216 as illustrated in FIG. 1B in some cases.

The conductor 205 a is formed in contact with an inner wall of the opening in the insulator 216, and the conductor 205 b is formed on the inner side. Here, the top surfaces of the conductors 205 a and 205 b can be at substantially the same level as the top surface of the insulator 216. The conductor 205 can function as one of two gate electrodes.

Moreover, a conductor 207 may be provided in a manner similar to that of the conductor 205. The conductor 207 is provided in the opening formed in the insulator 210, the insulator 212, the insulator 214, and the insulator 216. Part of the conductor 207 formed in the same layer as the insulator 216 functions as a wiring and part of the conductor 207 formed in the same layer as the insulator 210, the insulator 212, and the insulator 214 functions as a plug. As the conductor 207, a conductor 207 a is formed in contact with the inner wall of the opening and a conductor 207 b is formed inside the opening with the conductor 207 a provided therein. Here, the top surfaces of the conductors 207 a and 207 b can be at substantially the same level as the top surface of the insulator 216. The conductor 207 can be connected to a wiring, a circuit element, a semiconductor element, or the like positioned under the insulator 210. Moreover, when a similar wiring and a similar plug are provided over the conductor 207, the conductor 207 can be connected to a wiring, a circuit element, a semiconductor element, or the like positioned over the conductor 207.

The conductors 205 a and 207 a are preferably formed using a conductive material that is less likely to transmit impurities such as water or hydrogen, and for example, are preferably formed using tantalum, tantalum nitride, ruthenium, or ruthenium oxide, and may be a single layer or a stack. Accordingly, diffusion of impurities such as water or hydrogen from a layer under the insulator 210 into a layer over the insulator 210 through the conductor 205 or 207 can be inhibited. Note that it is preferable that at least one of impurities such as a hydrogen atom, a hydrogen molecule, a water molecule, an oxygen atom, an oxygen molecule, a nitrogen atom, a nitrogen molecule, a nitrogen oxide molecule (e.g., N₂O, NO, and NO₂), and a copper atom and oxygen (e.g., an oxygen atom or an oxygen molecule) be less likely to penetrate the conductors 205 a and 207 a. Furthermore, hereinafter, the same applies to the description of a conductive material that is less likely to transmit impurities.

When the conductors 205 b and 207 b are formed using a metal such as copper that easily diffuses into silicon oxide, diffusion of impurities such as copper into a layer over the insulator 220 can be prevented by using an insulating material such as silicon nitride or silicon nitride oxide that is less likely to transmit copper for the insulator 220. At this time, the conductors 205 a and 207 a are also preferably formed using a conductive material that is less likely to transmit copper so as to prevent diffusion of impurities into the outside of the conductors 205 a and 207 a.

The insulator 222 is preferably formed using an insulating material that is less likely to transmit oxygen and impurities such as water or hydrogen, and for example, is preferably formed using aluminum oxide or hafnium oxide. Accordingly, diffusion of impurities such as water or hydrogen from a layer under the insulator 210 into a layer over the insulators 212 and 214 can be inhibited. Furthermore, oxygen contained in the insulator 224 or the like can be inhibited from diffusing into lower layers.

The insulator 224 is preferably formed using an insulator from which oxygen is released by heating. Specifically, it is preferable to use an insulator with the following characteristics: the amount of oxygen that is released from the insulator in thermal desorption spectroscopy (TDS) and converted into oxygen atoms is 1.0×10¹⁸ atoms/cm³ or more, preferably 3.0×10²⁰ atoms/cm³ or more. Note that oxygen released by heating is also referred to as excess oxygen. When the insulator 224 formed using such an insulator is formed in contact with the oxide 230, oxygen can be supplied to the oxide 230 b effectively.

Furthermore, the concentration of impurities such as water, hydrogen, or nitrogen oxide in the insulator 224 is preferably lowered. The amount of hydrogen released from the insulator 224 that is converted into hydrogen molecules per area of the insulator 224 is less than or equal to 2×10¹⁵ molecules/cm², preferably less than or equal to 1×10¹⁵ molecules/cm², further preferably less than or equal to 5×10¹⁴ molecules/cm² in TDS analysis in the range of 50° C. to 500° C., for example.

The insulators 220, 222, and 224 serve as a gate insulating film.

The oxide 230 a is preferably formed using an oxide formed under an oxygen atmosphere, for example. Thus, the shape of the oxide 230 a can be stable. Note that the components of the oxides 230 a to 230 c are described in detail later.

In order to give stable electrical characteristics and favorable reliability to the transistor 200, it is preferable that the concentration of impurities and oxygen vacancies in the oxide be reduced so that the oxide 230 b is highly purified and intrinsic or substantially highly purified and intrinsic. The highly purified and intrinsic or substantially highly purified and intrinsic oxide has a low density of defect states and accordingly has a low density of trap states in some cases.

Charge trapped by the trap states in the oxide takes a long time to be released and may behave like fixed charge. Thus, a transistor whose channel region is formed in an oxide having a high density of trap states has unstable electrical characteristics and low reliability in some cases.

In order to obtain stable electrical characteristics and high reliability of the transistor, it is effective to reduce oxygen vacancies and the concentration of impurities in the oxide. In addition, in order to reduce the concentration of impurities in the oxide, the concentration of impurities in a film that is adjacent to the oxide is preferably reduced.

For the oxide 230 b, an oxide having an electron affinity higher than that of each of the oxides 230 a and 230 c is used. For example, as the oxide 230 b, an oxide having a higher electron affinity than the oxides 230 a and 230 c by 0.07 eV or more and 1.3 eV or less, preferably 0.1 eV or more and 0.7 eV or less, further preferably 0.15 eV or more and 0.4 eV or less is used. Note that the electron affinity refers to an energy difference between the vacuum level and the conduction band minimum.

The oxide 230 b includes a first region, a second region, and a third region. In the top view, the third region is positioned between the first region and the second region. The transistor 200 includes the conductive oxide 241 a over and in contact with the first region of the oxide 230 b, and includes the conductor 240 a over and in contact with the conductive oxide 241 a. Furthermore, the transistor 200 includes the conductive oxide 241 b over and in contact with the second region of the oxide 230 b, and includes the conductor 240 b over and in contact with the conductive oxide 241 b. The conductor 240 a and the conductive oxide 241 a can function as one of a source electrode and a drain electrode, and the conductor 240 b and the conductive oxide 241 b can function as the other of the source electrode and the drain electrode. Thus, one of the first and second regions of the oxide 230 b can function as the source region and the other can function as the drain region. The third region of the oxide 230 b can function as a channel formation region.

The conductive oxides 241 a and 241 b preferably have an effect of gettering impurities such as water or hydrogen in the oxide 230 b or from an insulator in the vicinity of the oxide 230 b, or the like (this effect is also referred to as getter action in some cases). Note that the conductive oxides 241 a and 241 b preferably have at least an effect of absorbing hydrogen atoms or hydrogen molecules; however, the conductive oxides 241 a and 241 b may have, for example, an effect of absorbing other impurities such as water molecules.

For the conductive oxides 241 a and 241 b, for example, indium tin oxide (ITO), indium tin oxide to which silicon is added, or indium zinc oxide can be used. Alternatively, indium oxide containing tungsten, indium zinc oxide containing tungsten, indium oxide containing titanium, or indium tin oxide containing titanium may be used. Indium gallium zinc oxide containing nitrogen may be used. A stack of a plurality of oxides formed using the above materials may be used.

Here, the conductive oxides 241 a and 241 b are formed of a metal oxide, and oxygen vacancies of the metal oxide, or the like can trap hydrogen. For example, by making the conductive oxides 241 a and 241 b include a larger number of oxygen vacancies, a larger amount of hydrogen can be gettered. In particular, the number of oxygen vacancies in the conductive oxides 241 a and 241 b is preferably larger than that in the oxide 230 b. With such a structure, the conductive oxides 241 a and 241 b can getter hydrogen efficiently from the oxide 230 b. At this time, the amount of hydrogen trapped by oxygen vacancies in the conductive oxides 241 a and 241 b is larger than that in the oxide 230 b in some cases.

Note that the number of oxygen vacancies included in the conductive oxide 241 a, the conductive oxide 241 b, and the oxide 230 b may be evaluated by a constant photocurrent method (CPM), for example. By the CPM, deep defect states due to oxygen vacancies in a sample can be evaluated. The amount of hydrogen trapped by oxygen vacancies included in the conductive oxide 241 a, the conductive oxide 241 b, and the oxide 230 b may be evaluated by electron spin resonance (ESR) analysis, for example. By the ESR, the conduction electrons due to hydrogen trapped by oxygen vacancies in a sample can be evaluated.

It is preferable that the conductive oxides 241 a and 241 b be able to hold hydrogen trapped by the oxygen vacancies at a temperature of higher than or equal to −40° C. and lower than or equal to 85° C., preferably higher than or equal to −40° C. and lower than or equal to 125° C. With such a structure, the conductive oxides 241 a and 241 b can getter impurities such as water or hydrogen included in an insulator in the vicinity of the conductive oxides 241 a and 241 b, or the like and in the oxide 230 b even after the completion of the semiconductor device. Moreover, the gettered hydrogen can be held in the conductive oxides 241 a and 241 b without being diffused into the oxide 230 b or the like.

When the conductive oxides 241 a and 241 b include a large number of oxygen vacancies or a large amount of hydrogen trapped by the oxygen vacancies, the resistivity of the conductive oxides 241 a and 241 b can be lowered. The resistivity of the conductive oxides 241 a and 241 b is preferably lower than that of the third region of the oxide 230 b. For example, the resistivity of the conductive oxides 241 a and 241 b is preferably lower than or equal to 1.0×10⁶ μΩcm, further preferably lower than or equal to 1.0×10⁵ μΩcm. With such a structure, the on-state current of the transistor 200 can be improved.

The conductive oxides 241 a and 241 b preferably form ohmic contact with the oxide 230 b. In order to form the ohmic contact, the conductive oxides 241 a and 241 b preferably contain at least one element that is the same as that of the oxide 230 b, further preferably two or more elements that are the same as those of the oxide 230 b. With such a structure, mixed layers having low densities of defect states can be formed between the conductive oxide 241 a and the oxide 230 b and between the conductive oxide 241 b and the oxide 230 b, so that the ohmic contact can be easily formed.

Furthermore, the conductive oxide 241 a (the conductive oxide 241 b) preferably forms ohmic contact with the conductor 240 a (the conductor 240 b). In order to form the ohmic contact, the conductors 240 a and 240 b are preferably a conductor capable of adding impurities such as nitrogen to the conductive oxides 241 a and 241 b when formed by a sputtering method to increase the carrier density of the conductive oxides 241 a and 241 b. For example, titanium nitride is preferably used for the conductors 240 a and 240 b. When the conductive oxides 241 a and 241 b include a large number of oxygen vacancies as described above, absorption of oxygen from the conductive oxide 241 a (the conductive oxide 241 b) by the conductor 240 a (the conductor 240 b) can be reduced. Thus, oxidization of the conductors 240 a and 240 b, which increases the resistance of the conductors 240 a and 240 b, can be prevented.

Note that when the conductive oxides 241 a and 241 b have a stacked-layer structure, layers below the conductive oxides 241 a and 241 b may be formed using a material that easily forms ohmic contact with the oxide 230 b, and layers over the conductive oxides 241 a and 241 b may be formed using a material that easily forms ohmic contact with the conductors 240 a and 240 b.

Here, side surfaces, which are in contact with the oxide 230 c, of the conductors 240 a and 240 b and the conductive oxides 241 a and 241 b each preferably have a taper angle of less than 90°. The angle formed between the bottom surface and each of the side surfaces, which are in contact with the oxide 230 c, of the conductors 240 a and 240 b and the conductive oxides 241 a and 241 b is preferably 45° or greater and 75° or less. When the conductors 240 a and 240 b and the conductive oxides 241 a and 241 b are formed to have such a structure, the oxide 230 c can be formed with good coverage also in step portions formed by the conductor 240. Accordingly, for example, disconnection of the oxide 230 c, which causes contact of the insulator 250 or the like to the oxide 230 b, can be prevented.

Moreover, the layer 245 a and the layer 245 b are formed over the conductor 240 a and the conductor 240 b, respectively. Here, for the layers 245 a and 245 b, a material that is less likely to transmit oxygen is preferably used, and aluminum oxide or the like can be used, for example. Accordingly, surrounding excess oxygen can be prevented from being used for oxidation of the conductors 240 a and 240 b.

The oxide 230 c is formed over the layers 245 a and 245 b, the conductors 240 a and 240 b, the conductive oxides 241 a and 241 b, and the oxide 230 b. Here, the oxide 230 c is in contact with the top surface of the oxide 230 b, side surfaces of the oxide 230 b in the channel width direction, side surfaces of the oxide 230 a in the channel width direction, and a top surface of the insulator 224. The oxide 230 c may have a function of supplying oxygen to the oxide 230 b. In addition, impurities such as water or hydrogen from the insulator 250 can be prevented from directly entering the oxide 230 b by forming the insulator 250 over the oxide 230 c. Furthermore, the oxide 230 c is preferably formed using an oxide formed under an oxygen atmosphere, for example; thus, the shape of the oxide 230 c can be stable.

The insulator 250 can function as a gate insulating layer. Like the insulator 224, the insulator 250 is preferably formed using an insulator from which oxygen is released by heating. When the insulator 250 formed using such an insulator is formed in contact with the oxide 230, oxygen can be supplied to the oxide 230 b effectively. Furthermore, like the insulator 224, the concentration of impurities such as water or hydrogen in the insulator 250 is preferably lowered.

The conductor 260 a is formed over the insulator 250. The conductor 260 b is formed over the conductor 260 a. The conductor 260 c is formed over the conductor 260 b. The insulator 250 and the conductor 260 each have a portion overlapping with the third region. In addition, end portions of the insulator 250, the conductor 260 a, the conductor 260 b, and the conductor 260 c are substantially aligned.

One of the conductor 205 and the conductor 260 can function as a front gate electrode and the other can function as a back gate electrode. The gate electrode and the back gate electrode are provided with the channel formation region in the semiconductor positioned therebetween. The potential of the back gate electrode may be the same as that of the gate electrode or may be a ground potential or a predetermined potential. By changing the potential of the back gate electrode independently of the potential of the gate electrode, the threshold voltage of the transistor can be changed.

The conductor 260 a is preferably an oxide having conductivity. For example, an In—Ga—Zn-based oxide having high conductivity and having an atomic ratio of [In]:[Ga]:[Zn]=4:2:3 to 4.1 or in the neighborhood thereof, which can be used as the oxide 230, is preferably used.

The conductor 260 b is preferably a conductor that can add impurities such as nitrogen to the conductor 260 a to improve the conductivity of the conductor 260 a. For example, titanium nitride is preferably used for the conductor 260 b.

Moreover, the layer 270 is formed over the conductor 260. Here, for the layer 270, a material that is less likely to transmit oxygen is preferably used, and aluminum oxide can be used, for example. Accordingly, surrounding excess oxygen can be prevented from being used for oxidation of the conductor 260. That is, the layer 270 functions as a gate cap for protecting the gate. The layer 270 and the oxide 230 c extend beyond end portions of the conductor 260 and have regions where the layer 270 and the oxide 230 c overlap with each other in the extending portions, and end portions of the layer 270 and the oxide 230 c are substantially aligned.

The insulator 272 is provided to cover the oxide 230, the conductive oxide 241, the conductor 240, the layer 245, the insulator 250, the conductor 260, and the layer 270. Furthermore, the insulator 272 is in contact with side surfaces of the oxide 230 b, side surfaces of the conductive oxide 241 a, side surfaces of the conductive oxide 241 b, and the top surface of the insulator 224. Furthermore, the insulator 274 is provided over the insulator 272. Each of the insulators 272 and 274 can function as a barrier insulating film for preventing impurities such as water or hydrogen from entering the transistor 200 and the like from a layer over the insulators 272 and 274.

Here, for the insulator 272, an oxide insulator that is formed by a sputtering method is preferably used, and for example, aluminum oxide is preferably used. With the insulator 272 formed using such an oxide insulator formed by a sputtering method, oxygen can be added to surfaces of the insulator 224 and the oxide 230 b that are in contact with the insulator 272, so that the insulator 224 and the oxide 230 b can be in an oxygen excess state.

The insulators 272 and 274 preferably getter hydrogen in the conductive oxide 241 a, the conductive oxide 241 b, the oxide 230, and the insulator 224 and diffuse the hydrogen outward by heat treatment. For example, the insulators 272 and 274 are preferably formed using aluminum oxide, in which case the concentration of impurities such as water or hydrogen in the conductive oxide 241, the insulator 224, and the oxide 230 b can be lowered. In the case where the conductive oxides 241 a and 241 b getter hydrogen from the oxide 230 b, the insulator 272 is provided in contact with the side surfaces of the conductive oxides 241 a and 241 b as described above, so that the trapped hydrogen can be exhausted outside the insulator 274.

Each of the insulators 272 and 274 is preferably formed using an insulating material that is less likely to transmit impurities such as water or hydrogen, and for example, are preferably formed using aluminum oxide. With the insulator 272 including the insulating material, impurities such as water or hydrogen can be inhibited from diffusing from a layer over the insulator 274 into a layer under the insulator 272.

Furthermore, for the insulator 274, an oxide insulator that is formed by an ALD method is preferably used, and for example, aluminum oxide is preferably used. The insulator 274 formed by an ALD method has favorable coverage, and is a film in which formation of cracks, pinholes, or the like are suppressed. Although the insulators 272 and 274 are provided over an uneven structure, the insulator 274 formed by an ALD method can cover the transistor 200 without occurrence of disconnection, formation of cracks and pinholes, or the like. Thus, even when disconnection or the like occurs in the insulator 272, the insulator 272 can be covered with the insulator 274; therefore, the barrier property against impurities such as water or hydrogen of a stacked film of the insulators 272 and 274 can be improved noticeably.

In the case where the insulator 272 is formed by a sputtering method and the insulator 274 is formed by an ALD method, when the thickness of a portion over the top surface of the conductor 260 c is referred to as a first thickness and the thickness of a portion over the side surfaces of the oxides 230 a and 230 b, the conductive oxide 241, and the conductor 240 is referred to as a second thickness, the ratio of the first thickness to the second thickness in the insulator 272 might be different from that in the insulator 274. In the insulator 272, the first thickness and the second thickness can be approximately the same thickness. In contrast, in the insulator 274, the first thickness tends to be greater than the second thickness; for example, the first thickness is approximately twice as large as the second thickness in some cases.

Furthermore, for the insulators 272 and 274, an insulating material that is less likely to transmit oxygen is preferably used. Accordingly, oxygen contained in the insulator 224, the insulator 250, or the like can be inhibited from diffusing upward.

As described above, when the transistor 200 is positioned between the insulators 274 and 272 and the insulators 214 and 212, a large amount of oxygen can be contained in the insulator 224, the oxide 230, and the insulator 250 without being diffused outward. Furthermore, impurities such as water or hydrogen can be prevented from entering from a layer over the insulator 274 and a layer under the insulator 212, and thus the concentration of impurities in the insulator 224, the oxide 230, and the insulator 250 can be lowered.

Since the conductive oxide 241 is in contact with the oxide 230 b, impurities such as water or hydrogen in the vicinity of the conductive oxide 241 can be gettered by the conductive oxide 241 to prevent impurities such as water or hydrogen from entering the oxide 230 b. Furthermore, impurities such as water or hydrogen in the oxide 230 b can also be gettered by the conductive oxide 241. Accordingly, the concentration of impurities in the oxide 230 b can be further lowered.

In this manner, oxygen vacancies in the oxide 230 b functioning as an active layer of the transistor 200 are reduced, and the concentration of impurities such as water or hydrogen is reduced; accordingly, the electrical characteristics of the transistor 200 are made stable, and the reliability can be improved.

An insulator 280 is provided over the insulator 274. Like the insulator 224 and the like, the concentration of impurities such as water or hydrogen in the insulator 280 is preferably lowered.

Moreover, an insulator 282 is provided over the insulator 280 and an insulator 284 is provided over the insulator 282. Each of the insulators 282 and 284 can function as a barrier insulating film for preventing impurities such as water or hydrogen from entering the transistor 200 and the like from a layer over the insulators 282 and 284. As well as the insulators 272 and 274, the insulators 282 and 284 are preferably formed using an insulating material that is less likely to transmit oxygen and impurities such as water or hydrogen, and for example, are preferably formed using aluminum oxide.

Like the insulators 272 and 274, the insulators 282 and 284 preferably have a property of gettering hydrogen in the insulator 280, and for example, is preferably formed using aluminum oxide. Providing the insulators 282 and 284 having such a property can lower the concentration of impurities such as water or hydrogen in the insulator 280.

Furthermore, like the insulator 274, for the insulator 284, an oxide insulator formed by an ALD method is preferably used, and for example, aluminum oxide is preferably used. With the insulator 284 including the insulating material, impurities such as water or hydrogen can be inhibited from diffusing from a layer over the insulator 284 into a layer under the insulator 282.

In the insulators 216, 220, 222, 224, 272, 274, and 280, an opening 480 is formed to reach the insulator 214. The insulator 282 is formed also on an inner wall of the opening 480 and in contact with the top surface of the insulator 214. Note that although only part of the opening 480 extending in the W1-W2 direction is illustrated in FIG. 1A, the opening 480 is formed to surround the transistors 200 and 400 and to surround at least the external side of the oxide 230. Moreover, it is preferable that the shape of the opening 480 seen from above be closed and a region inside the opening 480 and a region outside the opening 480 be divided. In the opening 480, the top surface of the insulator 214 and the bottom surface of the insulator 282 are in contact with each other; that is, a region surrounded by the opening 480 is a region surrounded by the insulators 214 and 282.

With such a structure, the transistor 200 can be surrounded and sealed with the insulators 282 and 284 in not only a perpendicular direction but also a lateral direction of the substrate. Accordingly, impurities such as water or hydrogen can be prevented from diffusing from the outside of the insulator 284 into the transistors 200 and 400. Moreover, the insulator 284 is formed without disconnection or the like even in the opening 480 when formed by an ALD method. Accordingly, even when disconnection or the like occurs in the insulator 282, it can be covered with the insulator 284; therefore, the barrier property of a stacked film of the insulators 282 and 284 against impurities can be improved.

In addition, the opening 480 is preferably formed inside dicing lines or scribe lines along which the semiconductor device 1000 is cut out. In this way, even when the semiconductor device 1000 is cut out, side surfaces of the insulator 280, the insulator 224, the insulator 216, and the like remain sealed with the insulators 282 and 284; therefore, impurities such as water or hydrogen can be prevented from diffusing from the insulators into the transistors 200 and 400. Note that a plurality of regions surrounded by the opening 480 may be provided inside the dicing lines or the scribe lines, and a plurality of semiconductor devices may be sealed with the insulators 282 and 284 separately.

Also after the completion of the semiconductor device, the conductive oxide 241 can getter impurities such as water or hydrogen included in an insulator in the vicinity of the conductive oxide 241 and in the oxide 230 b. Moreover, the gettered hydrogen can be held in the conductive oxide 241 without being diffused into the oxide 230 b or the like. Thus, even when slight impurities such as water or hydrogen continuously enter the transistor 200 over time after the completion of the semiconductor device, the impurities are gettered by the conductive oxide 241, so that the concentration of impurities in the oxide 230 b can be kept low. In such a manner, long-term reliability of the transistor 200 can be improved.

[Transistor 400]

As illustrated in FIGS. 1A, 1B, and 1E, the transistor 400 includes the insulator 212 over the insulator 210; the insulator 214 over the insulator 212; a conductor 403 (a conductor 403 a and a conductor 403 b), a conductor 405 (a conductor 405 a and a conductor 405 b), and a conductor 407 (a conductor 407 a and a conductor 407 b) that are over the insulator 214; the insulators 220, 222, and 224 over the conductors 403, 405, and 407; an oxide 430 over the insulator 224 and the conductors 405 b and 407 b; an insulator 450 over the oxide 430; a conductor 460 (a conductor 460 a, a conductor 460 b, and a conductor 460 c) over the insulator 450; a layer 470 over the conductor 460 c; the insulator 272 over the layer 470; and the insulator 274 over the insulator 272. Hereinafter, description of the components already made for the transistor 200 is omitted.

The conductors 403, 405, and 407 are provided in the openings in the insulator 216. The conductors 403, 405, and 407 preferably have a structure similar to that of the conductor 205. The conductor 403 a is formed in contact with an inner wall of the opening in the insulator 216, and the conductor 403 b is formed on the inner side. The conductors 405 and 407 also have a structure similar to that of the conductor 403. One of the conductor 405 and the conductor 407 can function as one of a source electrode and a drain electrode, and the other can function as the other of the source electrode and the drain electrode.

The oxide 430 preferably has a structure similar to that of the oxide 230 c. The oxide 430 includes a first region, a second region, and a third region. In the top view, the third region is positioned between the first region and the second region. The transistor 400 includes the conductors 405 b under the first region, and includes the conductor 407 b under the second region of the oxide 430. Thus, one of the first region and the second region of the oxide 430 can function as a source region and the other can function as a drain region. The third region of the oxide 430 can function as a channel formation region.

Note that although a channel is formed in the oxide 230 b in the transistor 200, a channel is formed in the oxide 430 in the transistor 400. The oxides 230 b and 430 are preferably formed using semiconductor materials having different electrical characteristics. When using semiconductor materials having different electrical characteristics, electrical characteristics of the transistor 200 and the transistor 400 can be different from each other.

Moreover, for example, when the oxide 430 is formed of a semiconductor having lower electron affinity than that of the oxide 230 b, the threshold voltage of the transistor 400 can be higher than that of the transistor 200. Specifically, when each of the oxide 430 and the oxide 230 b is an In-M-Zn oxide (an oxide containing In, an element M, and Zn) and when the oxide 430 has an atomic ratio of x₁:y₁:z₁ and the oxide 230 b is has an atomic ratio of x₂:y₂:z₂, y₁/x₁ needs to be larger than y₂/x₂. The atomic ratio of a target that is used for forming the oxide 230 b is preferably In:M:Zn=1:1:1, In:M:Zn=1:1:1.2, In:M:Zn=2:1:1.5, In:M:Zn=2:1:2.3, In:M:Zn=2:1:3, In:M:Zn=3:1:2, In:M:Zn=4:2:4.1, In:M:Zn=4:2:3, In:M:Zn=5:1:7, or the like. In addition, the atomic ratio of a target that is used for forming the oxide 430 is preferably In:M:Zn=1:2:4, In:M:Zn=1:3:2, In:M:Zn=1:3:4, In:M:Zn=1:3:6, In:M:Zn=1:3:8, In:M:Zn=1:4:3, In:M:Zn=1:4:4, In:M:Zn=1:4:5, In:M:Zn=1:4:6, In:M:Zn=1:6:3, In:M:Zn=1:6:4, In:M:Zn=1:6:5, In:M:Zn=1:6:6, In:M:Zn=1:6:7, In:M:Zn=1:6:8, In:M:Zn=1:6:9, In:M:Zn=1:10:1, or the like. However, not limited to this, the atomic ratios of the oxide 430 and the oxide 230 b may be determined as appropriate within the range satisfying the above condition. With such In-M-Zn oxides, the transistor 400 can have higher V_(th) than the transistor 200. The element M is aluminum, gallium, yttrium, tin, or the like. Other elements that can be used as the element M include boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium. Note that two or more of the above elements may be used in combination as the element M.

In addition, in the transistor 400, a channel formation region in the oxide 430 is in direct contact with the insulators 224 and 450, so that the transistor 400 is likely to be affected by interface scattering and the trap states. Thus, the transistor 400 can have lower field-effect mobility and carrier density. Furthermore, the transistor 400 can have higher V_(th) than the transistor 200.

The oxide 430 preferably contains much excess oxygen and is preferably formed using an oxide formed under an oxygen atmosphere, for example. By using the oxide 430 formed using such an oxide for an active layer, the threshold voltage of the transistor 400 can be higher than 0 V, the off-state current can be reduced, and I_(cut) can be noticeably reduced.

The insulator 450 preferably has a structure similar to that of the insulator 250 and can function as a gate insulating layer. When the insulator 450 formed using such an insulator is formed in contact with the oxide 430, oxygen can be supplied to the oxide 430 effectively. Furthermore, the concentration of impurities such as water or hydrogen in the insulator 450 is preferably lowered as in the insulator 224.

The conductor 460 preferably has a structure similar to that of the conductor 260. The conductor 460 a is formed over the insulator 450. The conductor 460 b is formed over the conductor 460 a. The conductor 460 c is formed over the conductor 460 b. The insulator 450 and the conductor 460 each have a portion overlapping with the third region. In addition, end portions of the insulator 450, the conductor 460 a, the conductor 460 b, and the conductor 460 c are substantially aligned. One of the conductor 403 and the conductor 460 can function as a front gate electrode and the other can function as a back gate electrode.

The layer 470 preferably has a structure similar to that of the layer 270. The layer 470 is formed over the conductor 460. Therefore, surrounding excess oxygen can be prevented from being used for oxidation of the conductor 460. The layer 470 and the oxide 430 extend beyond end portions of the conductor 460 and have regions where the layer 470 and the oxide 430 overlap with each other in the extending portions, and end portions of the layer 470 and the oxide 430 are substantially aligned.

Like the transistor 200, when the transistor 400 is positioned between the insulators 274 and 272 and the insulators 214 and 212, a large amount of oxygen can be contained in the insulator 224, the oxide 430, and the insulator 450 without being diffused outward. Furthermore, impurities such as water or hydrogen can be prevented from entering from a layer over the insulator 274 and a layer under the insulator 212, and thus the concentration of impurities in the insulator 224, the oxide 430, and the insulator 450 can be lowered.

In this manner, oxygen vacancies in the oxide 430 functioning as an active layer of the transistor 400 are reduced, and the concentration of impurities such as water or hydrogen is reduced; accordingly, the threshold voltage of the transistor 400 can be higher than 0 V, the off-state current can be reduced, and I_(cut) can be noticeably reduced. Moreover, the electrical characteristics of the transistor 400 are made stable, and the reliability can be improved.

With the structure in which the transistor 400 is used as a switching element so that the potential of the back gate of the transistor 200 can be retained, the off state of the transistor 200 can be maintained for a long time.

<Materials>

[Insulator]

The insulators 210, 216, 220, 224, 250, 450 and 280 may be formed, for example, with a single layer or a stack of layers of an insulating material containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum. The insulators 210, 216, 220, 224, 250, 450 and 280 may be formed, for example, with a single layer or a stack of layers of one or more materials selected from silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum nitride, aluminum oxide, aluminum nitride oxide, aluminum oxynitride, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, and aluminum silicate. Alternatively, a material in which two or more materials selected from an oxide material, a nitride material, an oxynitride material, and a nitride oxide material are mixed may be used.

Note that in this specification, a nitride oxide refers to a compound that contains more nitrogen than oxygen. An oxynitride refers to a compound that contains more oxygen than nitrogen. The content of each element can be measured by, for example, Rutherford backscattering spectrometry (RBS).

The insulators 212, 214, 222, 272, 274, 282, and 284 are preferably formed using an insulating material that is less likely to transmit impurities such as water or hydrogen than the insulators 224, 250, 450, and 280. Examples of such an insulating material that is less likely to transmit impurities include aluminum oxide, aluminum nitride, aluminum oxynitride, aluminum nitride oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, and silicon nitride. A single layer or a stack of any of these materials may be used.

When an insulating material that is less likely to transmit impurities is used for the insulators 212, 214, and 222, impurity diffusion from the substrate side into the transistor can be inhibited, and the reliability of the transistor can be improved. When an insulating material that is less likely to transmit impurities is used for the insulators 272, 274, 282, and 284, impurity diffusion from layers over the insulator 280 into the transistor can be inhibited, and the reliability of the transistor can be improved.

A plurality of insulating layers formed using any of the above-described materials may be stacked as each of the insulators 212, 214, 272, 282, and 284. One of the insulator 212 and the insulator 214 may be omitted. Moreover, one of the insulator 282 and the insulator 284 may be omitted.

An insulating material that is less likely to transmit impurities herein refers to a material having a high oxidation resistance and a function of inhibiting the diffusion of oxygen and impurities typified by hydrogen or water.

For example, the diffusion length of oxygen or hydrogen in aluminum oxide per hour under an atmosphere at 350° C. or 400° C. is much less than that in silicon oxide. Thus, it can be said that aluminum oxide is less likely to transmit impurities.

As an example of an insulating material that is less likely to transmit impurities, silicon nitride formed by a CVD method can be used. Here, diffusion of hydrogen into a semiconductor element including an oxide semiconductor, such as the transistor 200, degrades the characteristics of the semiconductor element in some cases. Therefore, the transistor 200 is preferably sealed with a film that inhibits hydrogen diffusion. Specifically, the film that inhibits hydrogen diffusion is a film from which hydrogen is less likely to be released.

The released amount of hydrogen can be measured by TDS, for example. The amount of hydrogen released from the insulator 212 that is converted into hydrogen molecules per unit area of the insulator 212 is less than or equal to 2×10¹⁵ molecules/cm², preferably less than or equal to 1×10¹⁵ molecules/cm², further preferably less than or equal to 5×10¹⁴ molecules/cm² in TDS analysis in the range from 50° C. to 500° C., for example.

Moreover, in particular, the dielectric constant of the insulators 216, 224, and 280 is preferably low. For example, the relative dielectric constant of the insulators 216, 224, and 280 is preferably lower than 3, further preferably lower than 2.4, still further preferably lower than 1.8. In the case where a material with a low dielectric constant is used as an interlayer film, the parasitic capacitance between wirings can be reduced. Furthermore, the insulators 216, 224, and 280 are preferably formed using an insulating material that is less likely to transmit impurities.

When an oxide semiconductor is used for the oxide 230, the concentration of hydrogen in the insulator is preferably lowered in order to prevent an increase in the concentration of hydrogen in the oxide 230. Specifically, the concentration of hydrogen in the insulator, which is measured by secondary ion mass spectrometry (SIMS), is lower than or equal to 2×10²⁰ atoms/cm³, preferably lower than or equal to 5×10¹⁹ atoms/cm³, further preferably lower than or equal to 1×10¹⁹ atoms/cm³, still further preferably lower than or equal to 5×10¹⁸ atoms/cm³. It is particularly preferable to lower the concentration of hydrogen in the insulators 216, 224 250, 450, and 280. It is preferable to lower the concentration of hydrogen in at least the insulators 224, 250, and 450 that are in contact with the oxide 230 or the oxide 430.

Furthermore, the nitrogen concentration in the insulator is preferably low in order to prevent an increase in the nitrogen concentration in the oxide 230. Specifically, the nitrogen concentration in the insulator, which is measured by SIMS, is lower than or equal to 5×10¹⁹ atoms/cm³, preferably lower than or equal to 5×10¹⁸ atoms/cm³, further preferably lower than or equal to 1×10¹⁸ atoms/cm³, still further preferably lower than or equal to 5×10¹⁷ atoms/cm³.

It is preferable that a region of the insulator 224 that is in contact with at least the oxide 230 and a region of the insulator 250 that is in contact with at least the oxide 230 have few defects and typically have as few signals observed by electron spin resonance (ESR) spectroscopy as possible. Examples of the signals include a signal due to an E′ center observed at a g-factor of 2.001. Note that the E′ center is due to the dangling bond of silicon. In the case where a silicon oxide layer or a silicon oxynitride layer is used as the insulators 224 and 250, a silicon oxide layer or a silicon oxynitride layer whose spin density due to the E′ center is lower than or equal to 3×10¹⁷ spins/cm³, preferably lower than or equal to 5×10¹⁶ spins/cm³ may be used.

In addition to the above-described signal, a signal due to nitrogen dioxide (NO₂) might be observed. The signal is divided into three signals according to the N nuclear spin; a first signal, a second signal, and a third signal. The first signal is observed at a g-factor of greater than or equal to 2.037 and less than or equal to 2.039. The second signal is observed at a g-factor of greater than or equal to 2.001 and less than or equal to 2.003. The third signal is observed at a g-factor of greater than or equal to 1.964 and less than or equal to 1.966.

It is suitable to use an insulating layer whose spin density due to nitrogen dioxide (NO₂) is higher than or equal to 1×10¹⁷ spins/cm³ and lower than 1×10¹⁸ spins/cm³ as the insulators 224 and 250, for example.

Note that nitrogen oxide (NO_(x)) such as nitrogen dioxide (NO₂) forms a state in the insulating layer. The level is positioned in the energy gap of the oxide semiconductor. Thus, when nitrogen oxide (NO_(x)) diffuses to the interface between the insulating layer and the oxide semiconductor, an electron can potentially be trapped by the level on the insulating layer side. As a result, the trapped electrons remain in the vicinity of the interface between the insulating layer and the oxide semiconductor; thus, the threshold voltage of the transistor is shifted in the positive direction. Therefore, a shift in the threshold voltage of the transistor can be reduced when a film with a low nitrogen oxide content is used as the insulators 224 and 250.

As an insulating layer that releases little nitrogen oxide (NO_(x)), for example, a silicon oxynitride layer can be used. The silicon oxynitride layer is a layer of which the amount of released ammonia is larger than the amount of released nitrogen oxide (NO_(x)) in TDS; the typical amount of released ammonia is greater than or equal to 1×10¹⁸/cm³ and less than or equal to 5×10¹⁹/cm³. Note that the released amount of ammonia is the total amount of ammonia released by heat treatment in a range from 50° C. to 650° C. or a range from 50° C. to 550° C. in TDS.

Since nitrogen oxide (NO_(x)) reacts with ammonia and oxygen in heat treatment, the use of an insulating film that releases a large amount of ammonia reduces nitrogen oxide (NO_(x)).

At least one of the insulators 216, 224, 250, and 450 is preferably formed using an insulating layer from which oxygen is released by heating. Specifically, it is preferable to use an insulator with the following characteristics: the amount of oxygen that is released from the insulator in TDS and converted into oxygen atoms is 1.0×10¹⁸ atoms/cm³ or more, preferably 3.0×10²⁰ atoms/cm³ or more.

The insulating layer containing excess oxygen can also be formed by performing treatment for adding oxygen to an insulating layer. The treatment for adding oxygen can be performed by heat treatment under an oxygen atmosphere, an ion implantation method, an ion doping method, a plasma immersion ion implantation method, plasma treatment, or the like. The plasma treatment containing oxygen is preferably performed using an apparatus including a power source for generating high-density plasma using microwaves, for example. Alternatively, a power source for applying a radio frequency (RF) to a substrate side may be provided. The use of high-density plasma enables high-density oxygen radicals to be produced, and application of the RF voltage to the substrate side allows oxygen radicals generated by the high-density plasma to be efficiently introduced into a film to be processed. Alternatively, after plasma treatment using an inert gas with the apparatus, plasma treatment using oxygen in order to compensate released oxygen may be performed. As a gas for adding oxygen, an oxygen gas of ¹⁶O₂, ¹⁸O₂, or the like, a nitrous oxide gas, an ozone gas, or the like can be used. In this specification, the treatment for adding oxygen is also referred to as “oxygen doping treatment”.

In addition, by oxygen doping treatment, the crystallinity of the semiconductor can be improved, and impurities such as water or hydrogen can be removed, in some cases. That is, “oxygen doping treatment” can also be referred to as “impurity removal treatment”. In particular, when plasma treatment using oxygen is performed as oxygen doping treatment under a reduced pressure, the bond of hydrogen and the bond of water in the insulator to be processed or the oxide to be processed are cut; therefore, hydrogen and water are easily released. Accordingly, heating treatment is preferably performed in or after the plasma treatment. Moreover, when the heating treatment is performed twice before and after the plasma treatment, the concentration of impurities in a film to be processed can be reduced.

There is no particular limitation on the method for forming the insulator; depending on a material thereof, any of the following methods may be used: a sputtering method, an SOG method, spin coating, dipping, spray coating, a droplet discharging method (e.g., an ink-jet method), a printing method (e.g., screen printing or offset printing), or the like.

Any of the above insulating layers may be used as the layers 245 a, 245 b, 270, and 470. In the case where each of the layers 245 a, 245 b, 270, and 470 is an insulating layer, an insulating layer that is less likely to release oxygen and/or that is less likely to absorb oxygen is preferably used.

[Oxide Semiconductor]

An oxide semiconductor used as the oxides 230 and 430 preferably contains at least indium or zinc. In particular, indium and zinc are preferably contained. In addition, aluminum, gallium, yttrium, tin, or the like is preferably contained. Furthermore, one or more elements selected from boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, or the like may be contained.

Here, the case where an oxide semiconductor is InMZnO containing indium, an element M, and zinc is considered. The element M is aluminum, gallium, yttrium, tin, or the like. Other elements that can be used as the element M include boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium. Note that two or more of the above elements may be used in combination as the element M.

Moreover, the band gap of an oxide semiconductor is greater than or equal to 2 eV; thus, when each of the oxides 230 and 430 in which oxygen vacancies and the concentration of impurities are reduced as described above is used as an oxide semiconductor, a transistor with an extremely low off-state current can be achieved. Specifically, the off-state current per micrometer of channel width at room temperature (typically 25° C.) and at a source-drain voltage of 3.5 V can be lower than 1×10⁻²⁰ A, lower than 1×10⁻²² A, or lower than 1×10⁻²⁴ A. That is, the on/off ratio of the transistor can be greater than or equal to 20 digits and less than or equal to 150 digits. A transistor using an oxide semiconductor in the oxide 230 has high withstand voltage between its source and drain. Thus, a transistor with favorable reliability can be provided. In addition, a transistor with high output voltage and high withstand voltage can be provided. Moreover, a semiconductor device or the like with favorable reliability can be provided. Furthermore, a semiconductor device with high output voltage and high withstand voltage can be provided.

<Structure>

An oxide semiconductor is classified into a single crystal oxide semiconductor and a non-single-crystal oxide semiconductor. Examples of a non-single-crystal oxide semiconductor include a c-axis-aligned crystalline oxide semiconductor (CAAC-OS), a polycrystalline oxide semiconductor, a nanocrystalline oxide semiconductor (nc-OS), an amorphous-like oxide semiconductor (a-like OS), and an amorphous oxide semiconductor.

The CAAC-OS has c-axis alignment, its nanocrystals are connected in the a-b plane direction, and its crystal structure has distortion. Note that distortion refers to a portion where the direction of a lattice arrangement changes between a region with a uniform lattice arrangement and another region with a uniform lattice arrangement in a region where the nanocrystals are connected.

The shape of the nanocrystal is basically a hexagon but is not always a regular hexagon and is a non-regular hexagon in many cases. A pentagonal lattice arrangement, a heptagonal lattice arrangement, and the like are included in the distortion in some cases. Note that a clear crystal grain boundary cannot be observed even in the vicinity of distortion in the CAAC-OS. That is, a lattice arrangement is distorted so that formation of a crystal grain boundary is inhibited. This is probably because the CAAC-OS can tolerate distortion owing to a low density of arrangement of oxygen atoms in an a-b plane direction, a change in interatomic bond distance by substitution of a metal element, and the like.

The CAAC-OS tends to have a layered crystal structure (also referred to as a stacked-layer structure) in which a layer containing indium and oxygen (hereinafter, In layer) and a layer containing the element M, zinc, and oxygen (hereinafter, (M,Zn) layer) are stacked. Note that indium and the element M can be replaced with each other, and when the element M of the (M,Zn) layer is replaced by indium, the layer can also be referred to as an (In,M,Zn) layer. When indium of the In layer is replaced by the element M, the layer can also be referred to as an (In,M) layer.

In the nc-OS, a microscopic region (for example, a region with a size greater than or equal to 1 nm and less than or equal to 10 nm, in particular, a region with a size greater than or equal to 1 nm and less than or equal to 3 nm) has a periodic atomic arrangement. There is no regularity of crystal orientation between different nanocrystals in the nc-OS. Thus, the orientation of the whole film is not observed. Accordingly, in some cases, the nc-OS cannot be distinguished from an a-like OS or an amorphous oxide semiconductor, depending on an analysis method.

The a-like OS has a structure between those of the nc-OS and the amorphous oxide semiconductor. The a-like OS has a void or a low-density region. That is, the a-like OS has low crystallinity as compared with the nc-OS and the CAAC-OS.

An oxide semiconductor can have various structures that show various different properties. Two or more of the amorphous oxide semiconductor, the polycrystalline oxide semiconductor, the a-like OS, the nc-OS, and the CAAC-OS may be included in an oxide semiconductor of one embodiment of the present invention.

<Atomic Ratio>

Next, preferred ranges of the atomic ratio of indium, the element M, and zinc contained in an oxide semiconductor according to the present invention are described with reference to FIGS. 25A to 25C. Note that the proportion of oxygen atoms is not illustrated in FIGS. 25A to 25C. The terms of the atomic ratio of indium, the element M, and zinc contained in the oxide semiconductor are denoted by [In], [M], and [Zn], respectively.

In FIGS. 25A to 25C, broken lines indicate a line where the atomic ratio [In]:[M]:[Zn] is (1+α):(1−α):1 (−1≤α≤1), a line where the atomic ratio [In]:[M]:[Zn] is (1+α):(1−α):2, a line where the atomic ratio [In]:[M]:[Zn] is (1+α):(1−α):3, a line where the atomic ratio [In]:[M]:[Zn] is (1+α):(1−α):4, and a line where the atomic ratio [In]:[M]:[Zn] is (1+α):(1−α):5.

Dashed-dotted lines indicate a line where the atomic ratio [In]:[M]:[Zn] is 5:1:β (β≥0), a line where the atomic ratio [In]:[M]:[Zn] is 2:1:β, a line where the atomic ratio [In]:[M]: [Zn] is 1:1:β, a line where the atomic ratio [In]:[M]:[Zn] is 1:2:β, a line where the atomic ratio [In]:[M]:[Zn] is 1:3:β, and a line where the atomic ratio [In]:[M]:[Zn] is 1:4:β.

Furthermore, an oxide semiconductor with the atomic ratio of [In]:[Zn]=0:2:1 or a neighborhood thereof in FIGS. 25A to 25C tends to have a spinel crystal structure.

A plurality of phases (e.g., two phases or three phases) exist in the oxide semiconductor in some cases. For example, with an atomic ratio [In]:[M]:[Zn] that is close to 0:2:1, two phases of a spinel crystal structure and a layered crystal structure are likely to exist. In addition, with an atomic ratio [In]:[M]:[Zn] that is close to 1:0:0, two phases of a bixbyite crystal structure and a layered crystal structure are likely to exist. In the case where a plurality of phases exist in the oxide semiconductor, a grain boundary might be formed between different crystal structures.

A region A in FIG. 25A represents examples of the preferred ranges of the atomic ratio of indium, the element M, and zinc contained in an oxide semiconductor.

The oxide semiconductor containing indium in a higher proportion can have high carrier mobility (electron mobility). Thus, an oxide semiconductor having a high content of indium has higher carrier mobility than an oxide semiconductor having a low content of indium.

In contrast, when the indium content and the zinc content in an oxide semiconductor become lower, carrier mobility becomes lower. Thus, with an atomic ratio of [In]:[M]:[Zn]=0:1:0 and the vicinity thereof (e.g., a region C in FIG. 25C), insulation performance becomes better.

Accordingly, an oxide semiconductor of one embodiment of the present invention preferably has an atomic ratio represented by the region A in FIG. 25A. With the atomic ratio, a stacked-layer structure with high carrier mobility and a few grain boundaries is easily obtained.

An oxide semiconductor with an atomic ratio in the region A, particularly in a region B in FIG. 25B, is excellent because the oxide semiconductor easily becomes a CAAC-OS and has high carrier mobility.

The CAAC-OS is an oxide semiconductor with high crystallinity. In contrast, in the CAAC-OS, a reduction in electron mobility due to the grain boundary is less likely to occur because a clear grain boundary cannot be observed. Entry of impurities, formation of defects, or the like might decrease the crystallinity of an oxide semiconductor. This means that the CAAC-OS has small amounts of impurities and defects (e.g., oxygen vacancies). Thus, an oxide semiconductor including a CAAC-OS is physically stable. Therefore, the oxide semiconductor including a CAAC-OS is resistant to heat and has high reliability.

Note that the region B includes an atomic ratio of [In]:[M]:[Zn]=4:2:3 to 4:2:4.1 and the vicinity thereof. The vicinity includes an atomic ratio of [In]:[M]:[Zn]=5:3:4. Note that the region B includes an atomic ratio of [In]:[M]:[Zn]=5:1:6 and the vicinity thereof and an atomic ratio of [In]:[M]: [Zn]=5:1:7 and the vicinity thereof.

Note that the property of an oxide semiconductor is not uniquely determined by an atomic ratio. Even with the same atomic ratio, the property of an oxide semiconductor might be different depending on a formation condition. For example, in the case where the oxide semiconductor is formed with a sputtering apparatus, a film having an atomic ratio deviated from the atomic ratio of a target is formed. Depending on the substrate temperature in deposition, [Zn] in the film might be smaller than [Zn] in the target. Thus, the illustrated regions each represent an atomic ratio with which an oxide semiconductor tends to have specific characteristics, and boundaries of the regions A to C are not clear.

[Transistor Including Oxide Semiconductor]

Next, the case where the above-described oxide semiconductor is used for a transistor is described.

Note that when the oxide semiconductor is used for a transistor, carrier scattering or the like at a grain boundary can be reduced; thus, the transistor can have high field-effect mobility. In addition, the transistor can have high reliability.

An oxide semiconductor with a low carrier density is preferably used for the transistor. In order to reduce the carrier density of the oxide semiconductor film, the concentration of impurities in the oxide semiconductor film is reduced so that the density of defect states can be reduced. In this specification and the like, a state with a low concentration of impurities and a low density of defect states is referred to as a highly purified intrinsic or substantially highly purified intrinsic state. For example, an oxide semiconductor whose carrier density is lower than 8×10¹¹/cm³, preferably lower than 1×10¹¹/cm³, further preferably lower than 1×10¹⁰/cm³, and greater than or equal to 1×10⁻⁹/cm³ is used.

A highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor has a low density of defect states and accordingly has a low density of trap states in some cases.

Charge trapped by the trap states in the oxide semiconductor takes a long time to be released and may behave like fixed charge. Thus, a transistor whose channel region is formed in an oxide semiconductor having a high density of trap states has unstable electrical characteristics in some cases.

In order to obtain stable electrical characteristics of the transistor, it is effective to reduce the concentration of impurities in the oxide semiconductor. In addition, in order to reduce the concentration of impurities in the oxide semiconductor, the concentration of impurities in a film that is adjacent to the oxide semiconductor is preferably reduced. Examples of impurities include hydrogen, nitrogen, alkali metal, alkaline earth metal, iron, nickel, and silicon.

<Impurities>

Here, the influence of impurities in the oxide semiconductor is described.

When silicon or carbon that is one of Group 14 elements is contained in the oxide semiconductor, defect states are formed. Thus, the concentration of silicon or carbon in the oxide semiconductor and around an interface with the oxide semiconductor (measured by SIMS) is set lower than or equal to 2×10¹⁸ atoms/cm³, and preferably lower than or equal to 2×10¹⁷ atoms/cm³.

When the oxide semiconductor contains alkali metal or alkaline earth metal, defect states are formed and carriers are generated, in some cases. Thus, a transistor including an oxide semiconductor that contains alkali metal or alkaline earth metal is likely to be normally-on. Therefore, it is preferable to reduce the concentration of alkali metal or alkaline earth metal in the oxide semiconductor. Specifically, the concentration of alkali metal or alkaline earth metal in the oxide semiconductor measured by SIMS is set lower than or equal to 1×10¹⁸ atoms/cm³, and preferably lower than or equal to 2×10¹⁶ atoms/cm³.

When the oxide semiconductor contains nitrogen, the oxide semiconductor easily becomes n-type by generation of electrons serving as carriers and an increase of carrier density. Thus, a transistor whose semiconductor includes an oxide semiconductor that contains nitrogen is likely to be normally-on. For this reason, nitrogen in the oxide semiconductor is preferably reduced as much as possible; for example, the concentration of nitrogen in the oxide semiconductor, which is measured by SIMS, can be lower than 5×10¹⁹ atoms/cm³, preferably lower than or equal to 5×10¹⁸ atoms/cm³, further preferably lower than or equal to 1×10¹⁸ atoms/cm³, and still further preferably lower than or equal to 5×10¹⁷ atoms/cm³.

Hydrogen contained in an oxide semiconductor reacts with oxygen bonded to a metal atom to be water, and thus causes an oxygen vacancy, in some cases. Due to entry of hydrogen into the oxygen vacancy, an electron serving as a carrier is generated in some cases. Furthermore, in some cases, bonding of part of hydrogen to oxygen bonded to a metal atom causes generation of an electron serving as a carrier. Thus, a transistor including an oxide semiconductor that contains hydrogen is likely to be normally-on. Accordingly, it is preferable that hydrogen in the oxide semiconductor be reduced as much as possible. Specifically, the concentration of hydrogen in the oxide semiconductor measured by SIMS is set lower than 1×10²⁰ atoms/cm³, preferably lower than 1×10¹⁹ atoms/cm³, further preferably lower than 5×10¹⁸ atoms/cm³, and still further preferably lower than 1×10¹⁸ atoms/cm³.

When an oxide semiconductor with a sufficiently reduced concentration of impurities and sufficiently reduced oxygen vacancies is used for a channel formation region in a transistor, the transistor can have stable electrical characteristics and high reliability.

<Band Diagram>

Next, the case where the oxide semiconductor has a two-layer structure or a three-layer structure is described. A band diagram of a stacked-layer structure of an oxide semiconductor S1, an oxide semiconductor S2, and an oxide semiconductor S3 and insulators that are in contact with the stacked-layer structure, a band diagram of a stacked-layer structure of the oxide semiconductors S2 and S3 and insulators that are in contact with the stacked-layer structure, and a band diagram of a stacked-layer structure of the oxide semiconductors S1 and S2 and insulators that are in contact with the stacked-layer structure are described with reference to FIGS. 26A to 26C.

FIG. 26A is an example of a band diagram of a stacked-layer structure including an insulator I1, the oxide semiconductor S1, the oxide semiconductor S2, the oxide semiconductor S3, and an insulator I2 in a thickness direction. FIG. 26B is an example of a band diagram of a stacked-layer structure including the insulator I1, the oxide semiconductor S2, the oxide semiconductor S3, and the insulator I2 in a thickness direction. FIG. 26C is an example of a band diagram of a stacked-layer structure including the insulator I1, the oxide semiconductor S1, the oxide semiconductor S2, and the insulator I2 in a thickness direction. Note that for easy understanding, the band diagrams show the conduction band minimum (Ec) of each of the insulator I1, the oxide semiconductor S1, the oxide semiconductor S2, the oxide semiconductor S3, and the insulator I2.

The conduction band minimum of each of the oxide semiconductors S1 and S3 is closer to the vacuum level than that of the oxide semiconductor S2. Typically, a difference in the conduction band minimum between the oxide semiconductor S2 and each of the oxide semiconductors S1 and S3 is preferably greater than or equal to 0.15 eV or greater than or equal to 0.5 eV, and less than or equal to 2 eV or less than or equal to 1 eV. That is, it is preferable that the electron affinity of the oxide semiconductor S2 be higher than the electron affinity of each of the oxide semiconductors S1 and S3, and the difference between the electron affinity of each of the oxide semiconductors S1 and S3 and the electron affinity of the oxide semiconductor S2 be greater than or equal to 0.15 eV or greater than or equal to 0.5 eV, and less than or equal to 2 eV or less than or equal to 1 eV.

As shown in FIGS. 26A to 26C, the conduction band minimum of each of the oxide semiconductors S1 to S3 is gradually varied. In other words, the conduction band minimum is continuously varied or continuously connected. In order to obtain such a band diagram, the density of defect states in a mixed layer formed at the interface between the oxide semiconductors S1 and S2 or the interface between the oxide semiconductors S2 and S3 is preferably made low.

Specifically, when the oxide semiconductors S1 and S2 or the oxide semiconductors S2 and S3 contain the same element (as a main component) in addition to oxygen, a mixed layer having a low density of defect states can be formed. For example, in the case where the oxide semiconductor S2 is an In—Ga—Zn oxide semiconductor, it is preferable to use an In—Ga—Zn oxide semiconductor, a Ga—Zn oxide semiconductor, gallium oxide, or the like as each of the oxide semiconductors S1 and S3.

At this time, the oxide semiconductor S2 serves as a main carrier path. Since the density of defect states at the interface between the oxide semiconductors S1 and S2 and the interface between the oxide semiconductors S2 and S3 can be made low, the influence of interface scattering on carrier conduction is small, and high on-state current can be obtained.

When an electron is trapped in a trap state, the trapped electron behaves like fixed charge; thus, the threshold voltage of the transistor is shifted in a positive direction. The oxide semiconductors S1 and S3 can make the trap state apart from the oxide semiconductor S2. This structure can prevent the positive shift of the threshold voltage of the transistor.

A material whose conductivity is sufficiently lower than that of the oxide semiconductor S2 is used for the oxide semiconductors S1 and S3. In that case, the oxide semiconductor S2, the interface between the oxide semiconductors S1 and S2, and the interface between the oxide semiconductors S2 and S3 mainly function as a channel region. For example, an oxide semiconductor with high insulation performance and the atomic ratio represented by the region C in FIG. 25C may be used as the oxide semiconductors S1 and S3. Note that the region C illustrated in FIG. 25C represents atomic ratios [In]:[M]:[Zn] of 0:1:0, 1:3:2, and 1:3:4 and the vicinities thereof.

In the case where an oxide semiconductor with the atomic ratio represented by the region A is used as the oxide semiconductor S2, it is particularly preferable to use an oxide semiconductor with an atomic ratio where [M]/[In] is greater than or equal to 1, preferably greater than or equal to 2 as each of the oxide semiconductors S1 and S3. In addition, it is suitable to use an oxide semiconductor with sufficiently high insulation performance and an atomic ratio where [M]/([Zn]+[In]) is greater than or equal to 1 as the oxide semiconductor S3.

Note that the oxide 230 used for the transistor 200 has the above-described three layer structure in this embodiment; however, one embodiment of the present invention is not limited thereto. For example, a two-layer structure without one of the oxide 230 a and the oxide 230 c may be employed. Alternatively, a single layer structure using any one of the oxide 230 a, the oxide 230 b, and the oxide 230 c may be employed. Alternatively, a four-layer structure in which any one of the above-described semiconductors is provided below or over the oxide 230 a or below or over the oxide 230 c may be employed. Alternatively, an n-layer structure (n is an integer of 5 or more) may be employed in which any one of the semiconductors described as examples of the oxide 230 a, the oxide 230 b, and the oxide 230 c is provided in two or more of the following positions: over the oxide 230 a, under the oxide 230 a, over the oxide 230 c, and under the oxide 230 c.

In this specification and the like, a transistor in which an oxide semiconductor is used for a semiconductor where a channel is formed is also referred to as an “OS transistor”. In this specification and the like, a transistor in which silicon having crystallinity is used for a semiconductor where a channel is formed is also referred to as a “crystalline Si transistor”.

The crystalline Si transistor tends to obtain relatively high mobility as compared to the OS transistor. On the other hand, the crystalline Si transistor has difficulty in obtaining extremely small off-state current unlike the OS transistor. Thus, it is important that the semiconductor material used for the semiconductor be selected depending on the purpose and the usage. For example, depending on the purpose and the usage, the OS transistor and the crystalline Si transistor may be used in combination.

An indium gallium oxide has a small electron affinity and an excellent oxygen-blocking property. Therefore, the oxide 230 c preferably includes an indium gallium oxide. The gallium atomic ratio [Ga/(In+Ga)] is, for example, higher than or equal to 70%, preferably higher than or equal to 80%, further preferably higher than or equal to 90%.

Note that the oxide 230 a and 230 c may be gallium oxide. For example, when gallium oxide is used for the oxide 230 c, a leakage current generated between the conductor 205 and the oxide 230 can be reduced. In other words, the off-state current of the transistor 200 can be reduced.

In that case, when a gate voltage is applied, a channel is formed in the oxide 230 b having the highest electron affinity in the oxides 230 a, 230 b, and 230 c.

In order to give stable electrical characteristics and favorable reliability to the transistor including an oxide semiconductor, it is preferable that impurities and oxygen vacancies in the oxide semiconductor be reduced to highly purify the oxide semiconductor so that at least the oxide 230 b can be regarded as an intrinsic or substantially intrinsic oxide semiconductor. Furthermore, it is preferable that at least a channel formation region of the oxide 230 b be regarded as an intrinsic or substantially intrinsic semiconductor.

The layers 245 a, 245 b, 270, and 470 may be formed using a material and a method that are similar to those of the oxide 230 or the oxide 430. In the case where the layers 245 a, 245 b, 270, and 470 are formed using an oxide semiconductor, an oxide semiconductor that is less likely to release oxygen and/or that is less likely to absorb oxygen is preferably used.

[Conductive Oxide]

It is preferable that the conductive oxides 241 a and 241 b be each a metal oxide containing indium. For the conductive oxides 241 a and 241 b, for example, indium tin oxide, indium tin oxide to which silicon is added, or indium zinc oxide can be used. Alternatively, indium oxide containing tungsten, indium zinc oxide containing tungsten, indium oxide containing titanium, or indium tin oxide containing titanium may be used. Indium gallium zinc oxide containing nitrogen may be used. A stack of a plurality of oxides formed of the above materials may be used.

The conductive oxides 241 a and 241 b preferably contain excess indium. For example, the density of indium in the conductive oxides 241 a and 241 b is preferably higher than that in the oxide 230 b. With such a structure, a large number of oxygen vacancies are easily formed in the vicinity of indium in the conductive oxides 241 a and 241 b, so that the number of oxygen vacancies can be increased.

Note that the density of indium contained in the conductive oxide 241 a, the conductive oxide 241 b, and the oxide 230 b can be evaluated by, for example, energy dispersive X-ray spectroscopy (EDX) analysis that uses a transmission electron microscope (TEM), inductively coupled plasma mass spectrometry (ICP-MS) analysis, X-ray photoelectron spectroscopy (XPS) analysis, or Rutherford backscattering spectrometry analysis.

Furthermore, the conductive oxides 241 a and 241 b are preferably a metal oxide containing indium and zinc. In particular, when InMZnO containing indium, the element M, and zinc is used as the oxide 230 b as described above, indium and zinc are elements common among the conductive oxide 241 a, the conductive oxide 241 b, and the oxide 230 b, and thus mixed layers having low densities of defect states can be formed between the conductive oxide 241 a and the oxide 230 b and between the conductive oxide 241 b and the oxide 230 b.

The conductive oxides 241 a and 241 b may contain an element that lowers the crystallinity of a metal oxide containing indium or a metal oxide containing indium and zinc. For example, tin and/or silicon and the like may be contained. In this case, the crystallinity of the conductive oxides 241 a and 241 b is lowered, and thus the number of oxygen vacancies can be increased.

The conductive oxides 241 a and 241 b may contain an element that improves the conductivity of nitrogen or the like. In this case, as the conductive oxides 241 a and 241 b, oxynitride containing nitrogen, nitride oxide containing nitrogen, or the like is used in some cases.

[Conductor]

As a conductive material for forming the conductors 205, 207, 403, 405, 407, 240, 260, and 460, a material containing one or more metal elements selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, and the like can be used. Alternatively, a semiconductor having a high electric conductivity typified by polycrystalline silicon including an impurity element such as phosphorus, or silicide such as nickel silicide may be used.

A conductive material containing the above metal element and oxygen may be used. A conductive material containing the above metal element and nitrogen may be used. For example, a conductive material containing nitrogen such as titanium nitride or tantalum nitride may be used. Indium tin oxide (ITO), indium oxide containing tungsten, indium zinc oxide containing tungsten, indium oxide containing titanium, indium tin oxide containing titanium, indium zinc oxide, or indium tin oxide to which silicon is added, may be used. Alternatively, indium gallium zinc oxide containing nitrogen may be used.

A stack of a plurality of conductive layers formed with the above materials may be used. For example, a layered structure formed using a combination of a material containing any of the metal elements listed above and a conductive material containing oxygen may be used. Alternatively, a layered structure formed using a combination of a material containing any of the metal elements listed above and a conductive material containing nitrogen may be used. Alternatively, a layered structure formed using a combination of a material containing any of the metal elements listed above, a conductive material containing oxygen, and a conductive material containing nitrogen may be used.

The conductors 205 b, 207 b, 403 b, 405 b, and 407 b may be formed using, for example, a conductive material such as tungsten or polysilicon. The conductors 205 a, 207 a, 403 a, 405 a, and 407 a in contact with the insulator 214 can have a single-layer structure or a stacked-layer structure including a barrier layer (a diffusion prevention layer) formed using titanium, titanium nitride, tantalum nitride, or the like.

When an insulating material that is less likely to transmit impurities is used for the insulators 212 and 214, and a conductive material that is less likely to transmit impurities is used for the conductors 205 a, 207 a, 403 a, 405 a, and 407 a in contact with the insulators 212 and 214, diffusion of impurities into the transistors 200 and 400 can be further inhibited. Thus, the reliabilities of the transistors 200 and 400 can be further increased.

Any of the above conductive materials may be used as the layers 245 a, 245 b, 270, and 470. In the case where the layers 245 a, 245 b, 270, and 470 are formed using a conductive material, a conductive material that is less likely to release oxygen and/or that is less likely to absorb oxygen is preferably used.

[Substrate]

There is no particular limitation on a material used as a substrate as long as the material has heat resistance high enough to withstand at least heat treatment performed later. For example, a single crystal semiconductor substrate or a polycrystalline semiconductor substrate made of silicon, silicon carbide, or the like or a compound semiconductor substrate made of silicon germanium or the like can be used as the substrate. Alternatively, an SOI substrate, a semiconductor substrate on which a semiconductor element such as a strained transistor or a FIN-type transistor is provided, or the like can also be used. Alternatively, gallium arsenide, aluminum gallium arsenide, indium gallium arsenide, gallium nitride, indium phosphide, silicon germanium, or the like that can be used for a high-electron-mobility transistor (HEMT) may be used. That is, the substrate is not limited to a simple supporting substrate, and may be a substrate where a device such as a transistor is formed. In this case, at least one of the gate, the source, and the drain of the transistor 200 or the transistor 400 may be electrically connected to the above-described device.

Further alternatively, as the substrate, a glass substrate of barium borosilicate glass, aluminoborosilicate glass, or the like, a ceramic substrate, a quartz substrate, a sapphire substrate, or the like can be used. Note that a flexible substrate may also be used as the substrate. In the case where a flexible substrate is used, a transistor, a capacitor, or the like may be directly formed over the flexible substrate; or the transistor, the capacitor, or the like may be formed over a manufacturing substrate and then separated from the manufacturing substrate and transferred onto the flexible substrate. To separate and transfer the transistor, the capacitor, or the like from the manufacturing substrate to the flexible substrate, a separation layer may be provided between the manufacturing substrate and the transistor, the capacitor, or the like.

For the flexible substrate, for example, metal, an alloy, resin, glass, or fiber thereof can be used. The flexible substrate used as the substrate preferably has a lower coefficient of linear expansion because deformation due to an environment is suppressed. The flexible substrate used as the substrate is formed using, for example, a material whose coefficient of linear expansion is lower than or equal to 1×10⁻³/K, lower than or equal to 5×10⁻⁵/K, or lower than or equal to 1×10⁻⁵/K. Examples of the resin include polyester, polyolefin, polyamide (e.g., nylon or aramid), polyimide, polycarbonate, and acrylic. In particular, aramid is preferably used for the flexible substrate because of its low coefficient of linear expansion.

<Example of Method for Manufacturing Semiconductor Device 1000>

An example of a method for manufacturing the semiconductor device 1000 is described with reference to FIGS. 2A to 2E, FIGS. 3A to 3E, FIGS. 4A to 4E, FIGS. 5A to 5E, FIGS. 6A to 6E, FIGS. 7A to 7E, FIGS. 8A to 8E, FIGS. 9A to 9E, FIGS. 10A to 10E, FIGS. 11A to 11E, FIGS. 12A to 12E, FIGS. 13A to 13E, FIGS. 14A to 14E, FIGS. 15A to 15E, FIGS. 16A to 16E, FIGS. 17A to 17E, FIGS. 18A to 18E, FIGS. 19A to 19E, FIGS. 20A to 20E, FIGS. 21A to 21E, FIG. 22, FIG. 23, and FIG. 24. Here, FIGS. 2A to 2E to FIGS. 21A to 21E correspond to FIGS. 1A to 1E. Among FIGS. 2A to 2E to FIGS. 21A to 21E, each figure “A” illustrates the top view of the semiconductor device 1000. Each figure “B” illustrates a cross-sectional view of the transistor 200 and the transistor 400 in the channel length direction, which is taken along dashed-dotted line L1-L2 in the respective figures “A”. Each figure “C” illustrates a cross-sectional view of the transistor 200 in the channel width direction, which is taken along dashed-dotted line W1-W2 in the respective figures “A”. Each figure “D” illustrates a cross-sectional view of the transistor 200 in the channel width direction, which is taken along dashed-dotted line W3-W4 in the respective figures “A”. Each figure “E” illustrates a cross-sectional view of the transistor 400 in the channel width direction, which is taken along dashed-dotted line W5-W6 in the respective figures “A”.

Hereinafter, an insulating material for forming the insulators, a conductive material for forming the conductors, or a semiconductor material for forming the semiconductors can be formed by a sputtering method, a spin coating method, a chemical vapor deposition (CVD) method (including a thermal CVD method, a metal organic chemical vapor deposition (MOCVD) method, a plasma enhanced CVD (PECVD) method, a high density plasma CVD method, a low pressure CVD (LPCVD) method, an atmospheric pressure CVD (APCVD) method, and the like), an ALD method, a molecular beam epitaxy (MBE) method, or a pulsed laser deposition (PLD) method as appropriate.

By using the PECVD method, a high-quality film can be formed at a relatively low temperature. By using a deposition method that does not use plasma for deposition, such as the MOCVD method, the ALD method, or the thermal CVD method, a film can be formed with few defects because damage is not easily caused on a surface on which the film is formed.

In the case where a film is formed by an ALD method, a gas that does not contain chlorine is preferably used as a material gas.

First, over a substrate (not illustrated), the insulator 210, the insulator 212, the insulator 214, and the insulator 216 are formed in this order. In this embodiment, a single crystal silicon substrate (including a p-type semiconductor substrate or an n-type semiconductor substrate) is used as the substrate (see FIGS. 2A to 2E).

In this embodiment, aluminum oxide is formed by an ALD method as the insulator 212. A dense insulating layer including reduced defects such as cracks or pinholes or having a uniform thickness can be formed by an ALD method.

In this embodiment, aluminum oxide is formed by a sputtering method as the insulator 214. As described above, the insulator 216 is preferably an insulator containing excess oxygen. After the formation of the insulator 216, oxygen doping treatment may be performed.

Next, a resist mask is formed over the insulator 216 and openings corresponding to the conductor 205, the conductor 405, the conductor 403, and the conductor 407 are formed in the insulator 216. Moreover, an opening corresponding to the conductor 207 is formed in the insulators 210, 212, 214, and 216. The resist mask can be formed by a photolithography method, a printing method, an inkjet method, or the like as appropriate. Formation of the resist mask by a printing method, an inkjet method, or the like needs no photomask; thus, manufacturing cost can be reduced.

The formation of the resist mask by a photolithography method can be performed in such a manner that a photosensitive resist is irradiated with light through a photomask and part of the resist that has been exposed to light (or has not been exposed to light) is removed using a developing solution. Examples of light with which the photosensitive resist is irradiated include KrF excimer laser light, ArF excimer laser light, extreme ultraviolet (EUV) light, and the like. Alternatively, a liquid immersion technique may be employed in which light exposure is performed with a part between a substrate and a projection lens filled with liquid (e.g., water). An electron beam or an ion beam may be used instead of the above-mentioned light. Note that a photomask is not necessary in the case of using an electron beam or an ion beam. Note that a dry etching method such as ashing or a wet etching method using a dedicated stripper or the like can be used for removal of the resist mask. Both the dry etching method and the wet etching method may be used.

When the openings are formed, part of the insulator 214 is also etched in some cases. The insulators 210, 212, 214, and 216 can be removed by a dry etching method, a wet etching method, or the like. Both the dry etching method and the wet etching method may be used. The resist mask is removed after the formation of the openings.

Next, a conductive film to be the conductors 207 a, 205 a, 403 a, 405 a, and 407 a and a conductive film to be the conductors 207 b, 205 b, 403 b, 405 b, and 407 b are formed over the insulators 214 and 216. In this embodiment, a stacked layer of tantalum nitride and titanium nitride is formed by a sputtering method as the conductive film to be the conductors 207 a, 205 a, 403 a, 405 a, and 407 a. In addition, tungsten is formed by a sputtering method as the conductive film to be the conductors 207 b, 205 b, 403 b, 405 b, and 407 b.

Next, chemical mechanical polishing treatment (also referred to as “CMP treatment”) is performed to form the conductors 207 a, 207 b, 205 a, 205 b, 403 a, 403 b, 405 a, 405 b, 407 a, and 407 b (see FIGS. 3A to 3E). By CMP treatment, part of the conductive films is removed. At this time, part of a surface of the insulator 216 is also removed in some cases. By the CMP treatment, unevenness of a sample surface can be reduced, and coverage with an insulating layer or a conductive layer to be formed later can be increased.

The conductors 207, 205, 405, 403, and 407 can be formed at the same time by a dual damascene process. In this manner, the conductors 207, 205, 403, 405, and 407 are formed.

The insulator 220, the insulator 222, and the insulator 224 are formed in this order over the insulator 216 and the conductors 207, 205, 403, 405, and 407 (see FIGS. 4A to 4E). In this embodiment, hafnium oxide is formed as the insulator 220 by an ALD method and silicon oxide is deposited as the insulator 224 by a CVD method.

Here, the concentration of impurities such as water or hydrogen in the insulator 224 is preferably lowered. Thus, impurities such as water or hydrogen are preferably diffused outward by heat treatment in an inert gas atmosphere containing nitrogen, a rare gas, or the like. The details of the heat treatment are described below. The insulator 224 is preferably an insulating layer containing excess oxygen. Thus, oxygen doping treatment may be performed after the formation of the insulator 224.

Next, an oxide film 230A, an oxide film 230B, a conductive oxide film 241A, a conductive film 240A, a film 245A, and a conductive film 247A are formed in this order (see FIGS. 5A to 5E).

When the oxides 230 a and 230 b each include an oxide semiconductor, oxide films 230A and 230B to be the oxides 230 a and 230 b are preferably formed by a sputtering method because each of the oxides 230 a and 230 b can have a higher density. A rare gas (typically argon), oxygen, or a mixed gas of a rare gas and oxygen may be used as a sputtering gas. Alternatively, deposition may be performed while the substrate is heated.

In addition, increasing the purity of a sputtering gas is also necessary. For example, an oxygen gas or a rare gas used as a sputtering gas is a gas that is highly purified to have a dew point of −60° C. or lower, preferably −100° C. or lower. By using the sputtering gas that is highly purified, entry of moisture or the like into the oxides 230 a and 230 b can be prevented as much as possible.

In the case where the oxide films 230A and 230B are formed by a sputtering method, it is preferable that moisture in a deposition chamber of a sputtering apparatus be removed as much as possible. For example, with an adsorption vacuum evacuation pump such as cryopump, the deposition chamber is preferably evacuated to be a high vacuum state (to a degree of approximately 5×10⁻⁷ Pa to 1×10⁻⁴ Pa). In particular, the partial pressure of gas molecules corresponding to H₂O (gas molecules corresponding to m/z=18) in the deposition chamber in the standby mode of the sputtering apparatus is preferably lower than or equal to 1×10⁻⁵ Pa, further preferably lower than or equal to 5×10⁻⁵ Pa.

In this embodiment, the oxide film 230A is formed by a sputtering method. Oxygen or a mixed gas of oxygen and a rare gas is used as the sputtering gas. When the proportion of oxygen in the sputtering gas is increased, the amount of excess oxygen in the oxide film to be formed can be increased.

At the formation of the oxide film 230B, part of oxygen contained in the sputtering gas is supplied to the insulators 224, 222, and 216 in some cases. As the amount of oxygen contained in the sputtering gas increases, the amount of oxygen supplied to the insulators 224, 222, and 216 increases. Thus, excess-oxygen regions can be formed in the insulators 224, 222, and 216. Moreover, part of oxygen supplied to the insulators 224, 222, and 216 reacts with hydrogen left in the insulators 224, 222, and 216 to produce water and the water is released from the insulators 224, 222, and 216 by later heat treatment. Thus, the concentration of hydrogen in the insulators 224, 222 and 216 can be reduced.

The proportion of oxygen in the sputtering gas is preferably 70% or more, further preferably 80% or more, still further preferably 100%. When oxide containing excess oxygen is used for the oxide film 230A, oxygen can be supplied to the oxide 230 b by later heat treatment.

Next, the oxide film 230B is formed by a sputtering method. At this time, when the proportion of oxygen in the sputtering gas is higher than or equal to 1% and lower than or equal to 30%, preferably higher than or equal to 5% and lower than or equal to 20%, an oxygen-deficient oxide semiconductor is formed. A transistor including an oxygen-deficient oxide semiconductor can have relatively high field-effect mobility.

Note that when an oxygen-deficient oxide semiconductor is used as the oxide film 230B, an oxide film containing excess oxygen is preferably used as the oxide film 230A. After the formation of the oxide film 230B, oxygen doping treatment may be performed.

After the formation of the oxide films 230A and 230B, heat treatment is preferably performed. The details of the heat treatment are described below. In this embodiment, the heat treatment is performed at 400° C. in an oxygen atmosphere for one hour. Accordingly, oxygen is introduced into the oxide films 230A and 230B. Further preferably, heat treatment is performed at 400° C. in a nitrogen gas atmosphere for one hour before the heat treatment performed in an oxygen atmosphere. By performing the heat treatment in a nitrogen gas atmosphere first, impurities such as water or hydrogen contained in the oxide films 230A and 230B are released, so that the concentration of impurities in the oxide films 230A and 230B can be reduced.

Next, the conductive oxide film 241A is formed. The conductive oxide film 241A is preferably formed by a sputtering method. In this embodiment, indium oxide to which silicon is added, indium zinc oxide to which silicon is added, or the like is used. Here, a target used for formation of the conductive oxide film 241A preferably contains a large amount of indium. With such a target, the amount of indium contained in the conductive oxide film 241A can be increased, so that the number of oxygen vacancies in the conductive oxide film 241A can be increased. When the formation is performed in such a manner, the resistivity of the conductive oxide film 241A can be reduced.

The conductive oxide film 241A preferably has a low resistivity. For example, when a film of indium oxide to which silicon is added is formed as the conductive oxide film 241A with the substrate temperature set at room temperature, the volume fraction (flow rate) of the oxygen gas during the formation is set at 1 vol % or more and 35 vol % or less, preferably 2 vol % or more and 10 vol % or less, so that the conductive oxide film 241A having a low resistivity can be easily formed.

For example, when a film of indium zinc oxide is formed as the conductive oxide film 241A with the substrate temperature set at room temperature, the volume fraction (flow rate) of the oxygen gas during the formation is set at 0 vol % or more and 35 vol % or less, preferably 0 vol % or more and 30 vol % or less, so that the conductive oxide film 241A having a low resistivity can be easily formed.

When the conductive oxide film 241A is formed with a relatively low flow rate of oxygen as described above, the number of oxygen vacancies in the conductive oxide film 241A can be increased.

Since the conductive oxide film 241A is formed over and in contact with the oxide film 230B, impurities such as water or hydrogen in the oxide film 230B can be gettered. Furthermore, impurities such as water or hydrogen contained in a conductor and an insulator that are formed over the conductive oxide film 241A in later steps can also be gettered. Note that when hydrogen or the like is trapped by the conductive oxide film 241A, the characteristics of the conductive oxide film 241A, for example, resistivity, might be changed from those of the conductive oxide film 241A that is just formed.

Note that when the conductive oxide film 241A is formed in an atmosphere containing oxygen, oxygen is added to the oxide film 230B, so that the state of the oxide film 230B can be close to an oxygen excess state.

Next, the conductive film 240A is formed. In this embodiment, tantalum nitride is deposited by a sputtering method as the conductive film 240A. Tantalum nitride has high oxidation resistance and thus is preferable in the case where heat treatment is performed in a later step. When the conductive film 240A is formed by a sputtering method in such a manner, metal atoms such as tantalum are introduced in the vicinity of the surface of the conductive oxide film 241A. Accordingly, oxygen vacancies are formed in the vicinity of the surface of the conductive oxide film 241A, so that ohmic contact can be easily formed between the conductive film 240A and the conductive oxide film 241A.

Because the conductive film 240A is in contact with the conductive oxide film 241A, impurity elements are introduced to the surface of the conductive oxide film 241A in some cases. When impurities such as nitrogen are added to the conductive oxide film 241A, the conductivity of the conductive oxide film 241A can be improved. Note that impurity elements may be introduced by an ion implantation method, an ion doping method, a plasma immersion ion implantation method, plasma treatment using a gas containing impurity elements, or the like before the conductive film 240A is formed. Alternatively, impurity elements may be introduced by an ion implantation method or the like after the conductive film 240A is formed.

Next, the film 245A is formed. In this embodiment, aluminum oxide is formed by an ALD method as the film 245A. A dense film including reduced defects such as cracks or pinholes or having a uniform thickness can be formed by an ALD method.

The conductive film 247A serves as a hard mask for forming the conductor 240 a and the conductor 240 b in a later step. In this embodiment, tantalum nitride is used as the conductive film 247A.

Then, the film 245A and the conductive film 247A are processed by a photolithography method, whereby a film 245B and a conductive film 247B are formed (see FIGS. 6A to 6E). The film 245B and the conductive film 247B include an opening.

Note that when the opening is formed, the side surfaces on the opening sides of the film 245B and the conductive film 247B each preferably have a taper angle with respect to the top surface of the conductive film 240A. Note that the angle is 30° or more and 90° or less, preferably 45° or more and 80° or less. The formation of the opening is preferably performed using the minimum feature size. That is, the film 245B has the opening whose width is the minimum feature size.

Then, a resist mask 290 is formed over the film 245B and the conductive film 247B by a photolithography method (see FIGS. 7A to 7E).

Next, part of the conductive oxide film 241A, part of the conductive film 240A, part of the film 245B, and part of the conductive film 247B are selectively removed using the resist mask 290 as a mask, so that the conductive oxide film 241A, the conductive film 240A, the film 245B, and the conductive film 247B are processed into an island shape (see FIGS. 8A to 8E). In this manner, a conductive oxide film 241B having an island shape is formed from the conductive oxide film 241A, a conductive film 240B having an island shape is formed from the conductive film 240A, the layer 245 a and the layer 245 b are formed from the film 245B, and a conductor 247 a and a conductor 247 b are formed from the conductive film 247B. Note that when the width of the opening in the film 245B is the minimum feature size, the distance between the layer 245 a and the layer 245 b is the minimum feature size.

Note that the conductive oxide film 241A, the conductive film 240A, the film 245A, and the conductive film 247A can be removed by a dry etching method, a wet etching method, or the like. Both the dry etching method and the wet etching method may be used.

Subsequently, part of the oxide film 230A and part of the oxide film 230B are selectively removed using the conductive film 240B as a mask (see FIGS. 9A to 9E). At this time, part of the insulator 224 might be also removed. Then, the resist mask is removed; thus, the island-shaped oxides 230 a and 230 b can be formed.

Note that the removal of the oxide films 230A and 230B can be performed by a dry etching method, a wet etching method, or the like. Both the dry etching method and the wet etching method may be used.

Then, part of the conductive oxide film 241B and part of the conductive film 240B are selectively removed by a dry etching method using the layers 245 a and 245 b and the conductors 247 a and 247 b as masks. By the etching step, the conductive oxide film 241B is divided into the conductive oxide 241 a and the conductive oxide 241 b, and the conductive film 240B is divided into the conductor 240 a and the conductor 240 b (see FIGS. 10A to 10E).

As a gas for the dry etching, for example, any of a C₄F₆ gas, a C₂F₆ gas, a C₄F₈ gas, a CF₄ gas, a SF₆ gas, and a CHF₃ gas can be used alone or in combination. Alternatively, an oxygen gas, a helium gas, an argon gas, a hydrogen gas, or the like can be added to any of the above gases as appropriate. In particular, a gas with which an organic substance can be generated by plasma is preferably used. For example, it is preferable to use a C₄F₆ gas, a C₄F₈ gas, or a CHF₃ gas to which a helium gas, an argon gas, or a hydrogen gas is added as appropriate.

Here, the conductors 247 a and 247 b function as hard masks, and the conductors 247 a and 247 b are also removed as etching progresses.

Using a gas with which an organic substance can be generated, the conductive oxide film 241B and the conductive film 240B are etched while an organic substance is attached to the side surfaces of the layers 245 a and 245 b and the conductors 247 a and 247 b, whereby side surfaces, which are to be in contact with the oxide 230 c, of the conductive oxide 241 a, the conductor 240 a, the conductive oxide 241 b, and the conductor 240 b can be tapered.

The conductive oxide 241 a, the conductor 240 a, the conductive oxide 241 b, and the conductor 240 b function as a source electrode and a drain electrode of the transistor 200; thus, a distance from the conductive oxide 241 a and the conductor 240 a to the conductive oxide 241 b and the conductor 240 b can be referred to as a channel length of the transistor. That is, when the width of the opening in the film 245B is minimum feature size, the distance between the layers 245 a and 245 b is the minimum feature size; therefore, the gate line width and the channel length can be smaller than the minimum feature size.

The angle of the side surface of the opening in the film 245B can be controlled depending on the ratio of the etching rate of the conductive film 240B to the deposition rate of the organic substance attached to the side surfaces of the layers 245 a and 245 b. For example, if the ratio of the etching rate to the deposition rate of the organic substance is 1, the angle is 45°.

The ratio of the etching rate and the deposition rate of the organic substance is determined by setting etching conditions as appropriate depending on the gas to be used in the etching. For example, the ratio of the etching rate and the deposition rate of the organic substance can be controlled by using a mixed gas of a C₄F₈ gas and an argon gas and controlling the high-frequency power and the etching pressure of the etching apparatus.

When the conductive oxide 241 a, the conductor 240 a, the conductive oxide 241 b, and the conductor 240 b are formed by a dry etching method, impurities such as remaining components of an etching gas might be attached to an exposed part of the oxide 230 b. For example, when a chlorine-based gas is used as an etching gas, chlorine and the like are attached in some cases. Furthermore, when a hydrocarbon-based gas is used as an etching gas, carbon, hydrogen, and the like are attached in some cases. The impurities attached to the exposed surface of the oxide 230 b are preferably reduced. The impurities can be reduced by cleaning treatment using hydrofluoric acid, cleaning treatment using ozone, cleaning treatment using ultra violet rays, or the like. Note that different types of cleaning treatment may be combined.

Plasma treatment using an oxidizing gas may be performed. For example, plasma treatment using a nitrous oxide gas is performed. By the plasma treatment, the concentration of fluorine in the oxide 230 b can be lowered. Moreover, the plasma treatment is effective in removing an organic substance on the surface of the sample.

Oxygen doping treatment may be performed on the exposed oxide 230 b. Furthermore, heat treatment described later may be performed.

When processing is performed using the layers 245 a and 245 b as masks, an etching gas having relatively high etching selectivity of the conductive film 240B to the insulator 224 can be used. Therefore, even when the thickness of the insulator 224 is small, over-etching of the wiring layer positioned below the insulator can be prevented. In addition, when the thickness of the insulator 224 is small, a voltage is effectively applied from the conductor 205; therefore, the transistor with low power consumption can be provided.

Next, heat treatment is preferably performed to further reduce impurities such as water or hydrogen contained in the oxides 230 a and 230 b and to purify the oxides 230 a and 230 b.

Plasma treatment using an oxidizing gas may be performed before the heat treatment. For example, plasma treatment using a nitrous oxide gas is performed. By the plasma treatment, the fluorine concentration in the exposed insulating layer can be lowered. Moreover, the plasma treatment is effective in removing an organic substance on the surface of a sample.

For example, the heat treatment is performed under an inert gas atmosphere of nitrogen, a rare gas, or the like, an oxidizing gas atmosphere, or an ultra-dry air atmosphere (the moisture amount is 20 ppm (−55° C. by conversion into a dew point) or less, preferably 1 ppm or less, further preferably 10 ppb or less, in the case where the measurement is performed by a dew point meter in a cavity ring down laser spectroscopy (CRDS) system). Note that the oxidizing gas atmosphere refers to an atmosphere containing an oxidizing gas such as oxygen, ozone, or nitrogen oxide at 10 ppm or higher. The inert gas atmosphere refers to an atmosphere containing the oxidizing gas at lower than 10 ppm and is filled with nitrogen or a rare gas. The pressure during the heat treatment is not particularly limited; however, the heat treatment is preferably performed under a reduced pressure.

By the heat treatment, at the same time as the release of the impurities, oxygen contained in the insulator 224 is diffused into the oxides 230 a and 230 b and oxygen vacancies therein can be reduced. Note that the heat treatment may be performed in such a manner that heat treatment is performed in an inert gas atmosphere, and then another heat treatment is performed in an atmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more in order to compensate for desorbed oxygen. The heat treatment may be performed at any time after the oxides 230 a and 230 b are formed.

The heat treatment may be performed at a temperature higher than or equal to 250° C. and lower than or equal to 650° C., preferably higher than or equal to 300° C. and lower than or equal to 500° C. The treatment time is shorter than or equal to 24 hours. Heat treatment for over 24 hours is not preferable because the productivity is reduced. Note that in the case where a metal that is likely to be diffused by heating, such as Cu, is used for the conductor, the temperature of the heat treatment may be set to lower than or equal to 410° C., preferably lower than or equal to 400° C.

In this embodiment, after heat treatment is performed at 400° C. in a nitrogen gas atmosphere for one hour, heat treatment is performed at 400° C. in an oxygen gas atmosphere for one hour. By performing the heat treatment in a nitrogen gas atmosphere first, impurities such as water or hydrogen contained in the oxides 230 a and 230 b are released, so that the concentration of impurities in the oxides 230 a and 230 b is reduced. Then, by performing the heat treatment in an oxygen atmosphere next, oxygen is introduced into the oxides 230 a and 230 b.

Since part of an upper surface of the conductive film 240B is covered with the layers 245 a and 245 b at the heat treatment, oxidation caused from the upper surface can be prevented.

Next, openings are formed in the insulators 220, 222, and 224 by a photolithography method. Note that the openings are formed over the conductors 405 b and 407 b (see FIGS. 11A to 11E).

Next, an oxide film 230C to be the oxides 230 c and 430 are formed. In this embodiment, like the oxide film 230A, the oxide film 230C is formed using an oxide containing much excess oxygen. When an oxide containing excess oxygen is used for the oxide film 230C, oxygen can be supplied to the oxide 230 b by later heat treatment.

At the formation of the oxide film 230C, like the oxide 230 a, part of oxygen contained in the sputtering gas is supplied to the insulators 224, 222 and 216 to form an excess-oxygen region in some cases. Moreover, part of oxygen supplied to the insulators 224, 222, and 216 reacts with hydrogen left in the insulators 224, 222 and 216 to produce water and the water is released from the insulators 224, 222 and 216 by later heat treatment. Thus, the concentration of hydrogen in the insulators 224, 222 and 216 can be reduced.

Note that after the oxide film 230C is formed, either or both of oxygen doping treatment and heat treatment may be performed. By the heat treatment, oxygen contained in the oxides 230 a and 230 c can be supplied to the oxide 230 b. When oxygen is supplied to the oxide 230 b, oxygen vacancies in the oxide 230 b can be reduced. Thus, when an oxygen-deficient oxide semiconductor is used as the oxide 230 b, an oxide containing excess oxygen is preferably used as the oxide 230 c.

Part of the oxide film 230C is in contact with a channel formation region of the oxide 230 b. In addition, top and side surfaces of the channel formation region of the oxide 230 b are covered with the oxide film 230C. In such a manner, the oxide 230 b can be surrounded by the oxide 230 a and the oxide film 230C. By surrounding the oxide 230 b by the oxide 230 a and the oxide film 230C, diffusion of impurities into the oxide 230 b that is to be caused in a later step can be inhibited.

Next, an insulating film 250A is formed over the oxide film 230C (see FIGS. 12A to 12E). In this embodiment, silicon oxynitride is formed by a CVD method as the insulating film 250A. The insulating film 250A preferably contains excess oxygen. The insulating film 250A may be subjected to oxygen doping treatment. Moreover, heat treatment may be performed after the formation of the insulating film 250A.

Then, a conductive film 260A, a conductive film 260B, and a conductive film 260C are formed in this order (see FIGS. 13A to 13E). In this embodiment, a metal oxide deposited by a sputtering method is used as the conductive film 260A, a film of titanium nitride is used as the conductive film 260B, and a film of tungsten is used as the conductive film 260C. The conductive film 260A formed by a sputtering method can add oxygen to the insulating film 250A, and the insulating film 250A can be in an oxygen excess state. Thus, oxygen can be supplied from the insulating film 250A to the oxide 230 b effectively.

Next, part of the insulating film 250A and part of the conductive films 260A to 260C are selectively removed by a photolithography method, so that the insulator 250, the insulator 450, the conductor 260 a, the conductor 260 b, the conductor 260 c, the conductor 460 a, the conductor 460 b, and the conductor 460 c are formed (see FIGS. 14A to 14E).

Next, a film 270A to be processed into the layer 270 and the layer 470 in a later step is formed (see FIGS. 15A to 15E). The film 270A functions as a gate cap, and in this embodiment, is formed using aluminum oxide deposited by an ALD method.

The subsequent steps are described with reference to flowcharts of FIG. 22 and FIG. 23. The steps in FIG. 22 and the steps in FIG. 23 mainly relate to the formation of the insulators 272 and 274 and the formation of the insulators 282 and 284, respectively. As described above, in order to provide stable electrical characteristics and favorable reliability for the transistors 200 and 400, it is important to supply oxygen contained in the insulators 212, 214, 272, 274, 282, and 284 to the oxides 230 and 430 without diffusing the oxygen outward and to prevent impurities such as water or hydrogen from entering the transistors 200 and 400 from the outside. The flowcharts of FIG. 22 and FIG. 23 show the steps on the left sides and the effects of the steps on the behaviors of impurities such as water or hydrogen and oxygen on the right sides.

Then, part of the film 270A is selectively removed by a photolithography method, so that the layers 270 and 470 are formed. This step corresponds to Step S01 in the flowchart of FIG. 22. By forming the layer 270 over the conductor 260 in this manner, surrounding excess oxygen can be prevented from being used for oxidation of the conductor 260.

The layers 270 and 470 can be etched by a dry etching method, a wet etching method, or the like. In this embodiment, the layers 270 and 470 are formed by a dry etching method. At this time, although part of the oxide film 230C can be removed in some cases, a residue of the oxide film 230C is likely to be left on the side surfaces of the conductive oxides 241 a and 241 b and the oxides 230 a and 230 b, or the like.

Next, the oxide film 230C is etched using the layers 270 and 470 as masks (see FIGS. 16A to 16E). This step corresponds to Step S02 in the flowchart of FIG. 22. The etching treatment in this step is performed by a wet etching or the like and a wet etching using phosphoric acid is performed in this embodiment. By this treatment, the island-shaped oxide 230 c and the island-shaped oxide 430 are formed. Even when part of the oxide film 230C remains as a residue, the residue is removed, and accordingly the side surfaces of the conductive oxides 241 a and 241 b and the oxides 230 a and 230 b can be exposed.

Next, heat treatment is preferably performed. This step corresponds to Step S03 in the flowchart of FIG. 22. The above description can be referred to for the heat treatment. In this embodiment, after heat treatment is performed at 400° C. in a nitrogen gas atmosphere for one hour, heat treatment is performed at 400° C. in an oxygen atmosphere for one hour. By performing the heat treatment in a nitrogen gas atmosphere first, impurities such as water or hydrogen contained in the oxide 230 are released, so that the concentration of impurities in the oxide 230 is reduced. Then, by performing the heat treatment in an oxygen atmosphere next, oxygen is introduced into the oxide 230.

Subsequently, the substrate is carried into a deposition apparatus including a plurality of chambers, and heat treatment is performed in the chamber of the deposition apparatus. This step corresponds to Step S04 in the flowchart of FIG. 22. The heating atmosphere or the like of this heat treatment can be referred to for the conditions of the above heat treatment. For example, this heat treatment is preferably performed under an oxygen atmosphere and the pressure in the chamber is higher than or equal to 1.0×10⁻⁸ Pa and lower than or equal to 1000 Pa, preferably higher than or equal to 1.0×10⁻⁸ Pa and lower than or equal to 100 Pa, further preferably higher than or equal to 1.0×10⁻⁸ Pa and lower than or equal to 10 Pa, still further preferably higher than or equal to 1.0×10⁻⁸ Pa and lower than or equal to 1 Pa. The heating temperature may be higher than or equal to 100° C. and lower than or equal to 500° C., preferably higher than or equal to 200° C. and lower than or equal to 450° C. In addition, in the case where a metal that is likely to be diffused by heating, such as Cu, is used for the conductor, the temperature of the heat treatment may be set to lower than or equal to 410° C., preferably lower than or equal to 400° C. Note that the heating temperature is preferably higher than the substrate temperature in the formation of the insulator 272 described later.

In this embodiment, the heat treatment is performed under an oxygen atmosphere for about 5 minutes at a substrate temperature of 400° C. By this treatment, moisture such as adsorbed water can be removed before the insulator 272 is formed. Under an oxygen atmosphere in particular, the heat treatment can be performed without forming an oxygen vacancy in the oxide 230.

Then, the insulator 272 is formed by a sputtering method in a chamber of the above deposition apparatus that is different from the chamber in which the heat treatment is performed (see FIGS. 17A to 17E). This step corresponds to Step S05 in the flowchart of FIG. 22. The formation of the insulator 272 is successively performed following the heat treatment in Step S04 without exposure of the substrate to outside air. In this embodiment, the thickness of the insulator 272 is 5 nm or greater and 100 nm or less, preferably 5 nm or greater and 20 nm or less, further preferably 5 nm or greater and 10 nm or less, approximately.

The insulator 272 is preferably formed under an atmosphere containing oxygen by a sputtering method. In this embodiment, as the insulator 272, an aluminum oxide film is formed in an atmosphere containing oxygen by a sputtering method. Accordingly, oxygen can be added to surfaces in contact with the insulator 272 (the side surfaces of the oxides 230 a and 230 b, the top surface of the insulator 224, and the like) and the periphery, so that the insulator 272 can be in an oxygen excess state. Although the oxygen is added as an oxygen radical here, for example, the state of the oxygen at the time of being added is not limited thereto. The oxygen may be added as an oxygen atom, an oxygen ion, or the like. Heat treatment in a later step or the like can diffuse oxygen so that oxygen can be supplied to the oxide 230 b effectively.

The insulator 272 is preferably formed while the substrate is being heated. The substrate heating is preferably performed at higher than 100° C. and lower than or equal to 200° C. The substrate heating is further preferably performed at higher than or equal to 120° C. and lower than or equal to 150° C. By making the substrate temperature higher than 100° C., water in the oxide 230 can be removed. Furthermore, water can be prevented from adsorbing on the surface of the formed film. The temperature of the substrate heating is preferably as low as possible. When a film is formed at low temperature, impurities in a film in contact with the film formed at low temperature are gettered more in later heat treatment. For example, when the insulator 272 is formed at approximately 130° C., hydrogen contained in the insulator 224, the oxide 230 a, the oxide 230 b, or the like can be gettered by the insulator 272.

Even when impurities such as water or hydrogen are removed by the heat treatment in Step S04, if the substrate is exposed to outside air before the formation of the insulator 272, impurities such as water or hydrogen may enter the oxide 230 or the like again. However, as described in this embodiment, the formation of the insulator 272 is successively performed following the heat treatment in Step S04 in the same deposition apparatus without exposure of the substrate to outside air; accordingly, the transistors 200 and 400 can be covered with the insulator 272 without entry of impurities such as water or hydrogen. Moreover, the insulator 272 can contain a larger amount of oxygen when oxygen is added to a site formed by the release of impurities such as water or hydrogen by the heat treatment in Step S04. In the case where heat treatment and the formation of the insulator 272 are performed in different chambers of a multi-chamber deposition apparatus, the insulator 272 can be formed without being influenced by impurities such as water or hydrogen released by the heat treatment.

For the insulator 272, an insulating material that is less likely to transmit impurities such as water or hydrogen is preferably used, and aluminum oxide is used in this embodiment. When the insulator 272 is formed by a sputtering method, the insulator 272 can be formed at a greater deposition rate than that of the insulator 274, and thus a stacked film of the insulators 272 and 274 can have a large thickness with high productivity. In this manner, the insulators 272 and 274 can have high barrier property against impurities such as water or hydrogen with high productivity.

Next, the insulator 274 is formed over the insulator 272 by an ALD method (see FIGS. 18A to 18E). This step corresponds to Step S06 in the flowchart of FIG. 22. In this embodiment, the thickness of the insulator 274 is 5 nm or greater and 20 nm or less, preferably 5 nm or greater and 10 nm or less, further preferably 5 nm or greater and 7 nm or less.

The insulator 274 is preferably formed using an insulating material that is less likely to transmit impurities such as water or hydrogen, and for example, is preferably formed using aluminum oxide. When the insulator 274 is formed by an ALD method, formation of cracks, pinholes, or the like can be suppressed, and the insulator 274 can be formed with good coverage. Although the insulators 272 and 274 are formed over an uneven structure, by forming the insulator 274 by an ALD method, disconnection, cracks, pinholes, or the like are not formed, and the transistors 200 and 400 can be covered with the insulator 274. Thus, the barrier property against impurities such as water or hydrogen can be improved noticeably.

Since the transistors 200 and 400 are positioned between the insulators 274 and 272 and the insulators 214 and 212 in this manner, oxygen is prevented from diffusing into the outside and a large amount of oxygen can be contained in the insulator 224, the oxide 230, and the insulator 250. Furthermore, impurities such as water or hydrogen can be prevented from entering from a layer over the insulator 274 and a layer under the insulator 212, and thus the concentration of impurities in the insulator 224, the oxide 230, and the insulator 250 can be lowered.

Next, heat treatment is preferably performed. This step corresponds to Step S07 in the flowchart of FIG. 22. For the heat treatment, the above description can be referred to. In this embodiment, the heat treatment is performed at 400° C. in a nitrogen gas atmosphere for one hour.

By this heat treatment, oxygen added in Step S05 and the like and contained in the insulators 224, 250, and the like of the transistor 200 can be diffused. Therefore, oxygen vacancies in the oxides 230 a to 230 c can be reduced. Also in the transistor 400, oxygen contained in the insulators 224, 450, and the like can be diffused and supplied to the oxide 430, particularly to a channel formation region of the oxide 430. Here, the insulators 212, 214, 222, and 272 can prevent oxygen from diffusing over and under the transistors 200 and 400, and thus oxygen can be supplied to the oxides 230 b and 430 effectively.

FIG. 24 is a schematic view illustrating states of hydrogen and water in the vicinity of the side surface of the oxide 230 b (hereinafter, referred to as a region 299) when the heat treatment is performed. By the heat treatment, hydrogen contained in the insulator 224, the oxides 230 a and 230 b, the conductive oxide 241 a, the conductive oxide 241 b (not illustrated in FIG. 24), and the like is gettered by the insulators 272 and 274 and diffused outward from the upper side of the insulators 272 and 274 as water. Thus, the insulators 272 and 274 have a function of releasing hydrogen contained in the insulator 224, the oxide 230 a, the oxide 230 b, or the like outside the insulator 274 as water; therefore, the insulators 272 and 274 have an effect similar to that of a catalyst. That is, the insulators 272 and 274 have a catalytic effect. In this manner, the concentration of impurities such as water or hydrogen in the insulators 272 and 274, the oxides 230 a and 230 b, and the conductive oxides 241 a and 241 b can be further reduced.

As described above, by providing the insulator 272 in contact with the side surfaces of the conductive oxides 241 a and 241 b, the trapped hydrogen can be not only held but also released outside the insulator 274.

In this manner, oxygen vacancies in the oxide 230 b functioning as an active layer of the transistor 200 are reduced, and the concentration of impurities such as water or hydrogen is reduced; accordingly, the electrical characteristics of the transistor 200 are made stable, and the reliability can be improved.

Note that the heat treatment in Step S07 may be performed after the insulator 272 is formed in Step S05. When the insulator 272 is formed while the substrate is being heated in Step S05, the heat treatment in Step S07 can be omitted.

Then, the insulator 280 is formed over the insulator 274. This step corresponds to Step S11 in the flowchart of FIG. 23. In this embodiment, silicon nitride formed by a plasma CVD method is used for the insulator 280.

Next, CMP treatment is performed to reduce unevenness of a surface of the insulator 280 (see FIGS. 19A to 19E). This step corresponds to Step S12 in the flowchart of FIG. 23.

Then, the opening 480 is formed in the insulators 216, 220, 222, 224, 272, 274, and 280 to reach the insulator 214 (see FIGS. 20A to 20E). This step corresponds to Step S13 in the flowchart of FIG. 23. Note that although part of the opening 480 extending in the W1-W2 direction is illustrated in FIG. 21A, the opening 480 is formed to surround the transistors 200 and 400.

Here, the opening 480 is preferably formed inside dicing lines or scribe lines along which the semiconductor device 1000 is cut out. In this way, even when the semiconductor device 1000 is cut out, the side surfaces of the insulator 280, the insulator 224, the insulator 216, and the like remain sealed with the insulators 282 and 284 that are formed in later steps; therefore, impurities such as water or hydrogen can be prevented from diffusing from the insulators into the transistors 200 and 400. Note that a plurality of regions surrounded by the opening 480 may be provided inside the dicing lines or the scribe lines, and a plurality of semiconductor devices may be sealed with the insulators 282 and 284 separately.

Subsequently, like Step S04, the substrate is carried into the deposition apparatus including a plurality of chambers, and heat treatment is performed in the chamber of the deposition apparatus. This step corresponds to Step S14 in the flowchart of FIG. 23. By this treatment, moisture such as adsorbed water can be removed before the insulator 282 is formed.

Then, like Step S05, the insulator 282 is formed by a sputtering method in a chamber of the above deposition apparatus that is different from the chamber in which the heat treatment is performed. This step corresponds to Step S15 in the flowchart of FIG. 23. The formation of the insulator 282 is successively performed following the heat treatment in Step S14 without exposure of the substrate to outside air.

The insulator 282 is formed in contact with the top surface of the insulator 214 in the opening 480. Thus, the transistors 200 and 400 can be surrounded and sealed with the insulator 282 in not only a perpendicular direction but also a lateral direction of the substrate. Accordingly, impurities such as water or hydrogen can be prevented from diffusing from the outside of the insulator 282 into the transistors 200 and 400.

As described in this embodiment, when the formation of the insulator 282 is successively performed following the heat treatment in Step S14 in the same deposition apparatus without exposure of the substrate to outside air, the transistors 200 and 400 can be covered with the insulator 282 without entry of impurities such as water or hydrogen. Moreover, the insulator 282 can contain a larger amount of oxygen by adding oxygen to a site formed by the release of impurities such as water or hydrogen in the heat treatment in Step S14. In the case where heat treatment and the formation of the insulator 282 are performed in different chambers of a multi-chamber deposition apparatus, the insulator 282 can be formed without being influenced by impurities such as water or hydrogen released by the heat treatment.

Next, the insulator 284 is formed over the insulator 282 by an ALD method (see FIGS. 21A to 21E). This step corresponds to Step S16 in the flowchart of FIG. 23.

The insulator 284 is preferably formed using an insulating material that is less likely to transmit impurities such as water or hydrogen, and for example, is preferably formed using aluminum oxide. When the insulator 284 is formed by an ALD method, formation of cracks, pinholes, or the like can be suppressed, and the insulator 284 can be formed with good coverage. When the insulator 282 is formed by an ALD method, the insulator 282 can be formed without disconnection or the like even in the opening 480. Thus, the barrier property against impurities can be further improved.

Next, like Step S07, heat treatment is preferably performed. This step corresponds to Step S17 in the flowchart of FIG. 23. Like Step S07, by the heat treatment, hydrogen contained in the insulator 280 and the like can be gettered by the insulators 282 and 284 and diffused outward from the upper side of the insulator 284 as water. In this manner, the concentration of impurities such as water or hydrogen contained in the insulator 280 can be reduced. Note that the heat treatment in Step S17 may be performed after the formation of the insulator 284 in Step S15. In addition, in the case where formation is performed while the substrate is being heated in Step S15, the heat treatment in Step S17 can be omitted.

Through the above steps, the transistor 200, the transistor 400, and the semiconductor device 1000 are formed. By the above-described manufacturing method, the transistors 200 and 400 having different structures can be provided over the same substrate through substantially the same process. By the above-described manufacturing method, for example, since the transistor 400 is not necessarily manufactured after the transistor 200 is manufactured, the productivity of the semiconductor device can be increased.

In the transistor 200, a channel is formed in the oxide 230 b, which is in contact with the oxides 230 a and 230 c. In the transistor 400, a channel is formed in the oxide 430, which is in contact with the insulators 224 and 450. Thus, the transistor 400 is likely to be affected by interface scattering compared with the transistor 200. The electron affinity of the oxide 430 in this embodiment is lower than that of the oxide 230 b. Thus, the transistor 400 can have higher V_(th) than the transistor 200 and can have small I_(cut).

Modification Example

The structure of the semiconductor device in this embodiment is not limited to the structure in FIGS. 1A to 1E. For example, a structure in FIGS. 27A to 27E may be employed.

The semiconductor device 1000 in FIGS. 27A to 27E is different from the semiconductor device 1000 in FIGS. 1A to 1E in that the opening 480 is formed in the insulators 216, 220, 222, and 224 and the insulator 272 is in contact with the top surface of the insulator 214. Thus, the transistors 200 and 400 are sealed with the insulators 212, 214, 272, and 274. In this case, even when the insulators 282 and 284 are not provided, entry of impurities such as water or hydrogen from the side surfaces of the insulators 216 and 224 can be prevented.

Moreover, the semiconductor device 1000 in FIGS. 27A to 27E is different from the semiconductor device 1000 in FIGS. 1A to 1E in that the layer 270, the insulator 250, and the oxide 230 c extend beyond the end portions of the conductor 260 and overlap with each other in the extending portions, and end portions of the layer 270, the insulator 250, and the oxide 230 c are substantially aligned. In this structure, the insulator 272 and side surfaces of the insulator 250 are in contact with each other. Therefore, the insulator 272 can supply oxygen to the insulator 250. Furthermore, impurities such as water or hydrogen contained in the insulator 250 can be gettered by the insulator 272 and diffused outward.

As described above, one embodiment of the present invention can provide a semiconductor device having favorable reliability. Alternatively, according to one embodiment of the present invention, a semiconductor device including an oxide semiconductor in which the concentration of impurities is reduced can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device including an oxide semiconductor in which oxygen vacancies are reduced can be provided.

This embodiment can be implemented in an appropriate combination with any of the structures described in the other embodiments, example, and the like.

Embodiment 2

In this embodiment, embodiments of semiconductor devices are described with reference to FIG. 28, FIG. 29, and FIG. 30.

[Memory Device]

FIGS. 28 to 30 each illustrate an example of a memory device using the semiconductor device of one embodiment of the present invention.

The memory devices in FIG. 28 and FIG. 29 each include the transistor 400, a transistor 300, the transistor 200, and a capacitor 100. The transistors 200 and 400 are similar to those described in the Embodiment 1.

The transistor 200 is a transistor in which a channel is formed in a semiconductor layer including an oxide semiconductor. Since the off-state current of the transistor 200 is small, by using the transistor 200 in a memory device, stored data can be retained for a long time. In other words, such a memory device does not require refresh operation or has an extremely low frequency of the refresh operation, which leads to a sufficient reduction in power consumption of the memory device.

Moreover, supplying a negative potential to a back gate of the transistor 200 can further reduce the off-state current of the transistor 200. In that case, with a structure capable of maintaining the back gate voltage of the transistor 200, stored data can be retained for a long time without power supply.

The back gate voltage of the transistor 200 is controlled by the transistor 400. For example, a top gate and a back gate of the transistor 400 are diode-connected to a source thereof, and the source of the transistor 400 and the back gate of the transistor 200 are connected to each other. When the negative potential of the back gate of the transistor 200 is held in the structure, the top gate-source voltage and the back gate-source voltage of the transistor 400 are each 0 V. As described in the above embodiment, the I_(cut) of the transistor 400 is extremely small. Thus, the structure allows the negative potential of the back gate of the transistor 200 to be held for a long time without power supply to the transistor 200 and the transistor 400. Accordingly, the memory device including the transistor 200 and the transistor 400 can retain stored data for a long time.

In FIG. 28 and FIG. 29, a wiring 3001 is electrically connected to a source of the transistor 300, and a wiring 3002 is electrically connected to a drain of the transistor 300. A wiring 3003 is electrically connected to one of a source and a drain of the transistor 200, a wiring 3004 is electrically connected to a top gate of the transistor 200, and a wiring 3006 is electrically connected to the back gate of the transistor 200. A gate of the transistor 300 and the other of the source and the drain of the transistor 200 are electrically connected to one electrode of the capacitor 100. A wiring 3005 is electrically connected to the other electrode of the capacitor 100. A wiring 3007 is electrically connected to the source of the transistor 400, a wiring 3008 is electrically connected to the gate of the transistor 400, a wiring 3009 is electrically connected to the back gate of the transistor 400, and a wiring 3010 is electrically connected to the drain of the transistor 400. The wiring 3006, the wiring 3007, the wiring 3008, and the wiring 3009 are electrically connected to each other.

<Memory Device Configuration 1>

The memory devices in FIG. 28 and FIG. 29 have a feature that the potential of the gate of the transistor 300 can be held, and thus enables writing, retaining, and reading of data as follows.

Writing and retaining of data are described. First, the potential of the wiring 3004 is set to a potential at which the transistor 200 is on, so that the transistor 200 is turned on. Accordingly, the potential of the wiring 3003 is supplied to a node FG where the gate of the transistor 300 and the one electrode of the capacitor 100 are electrically connected to each other. That is, predetermined charge is supplied to the gate of the transistor 300 (writing). Here, one of two kinds of charge that provide different potential levels (hereinafter, referred to as low-level charge and high-level charge) is supplied. After that, the potential of the wiring 3004 is set to a potential at which the transistor 200 is off, so that the transistor 200 is turned off. Thus, the charge is retained in the node FG (retaining).

Since the off-state current of the transistor 200 is small, the charge of the node FG is retained for a long time.

Next, reading of data is described. An appropriate potential (reading potential) is supplied to the wiring 3005 while a predetermined potential (constant potential) is supplied to the wiring 3001, whereby the potential of the wiring 3002 varies depending on the amount of charge retained in the node FG. This is because in the case of using an n-channel transistor as the transistor 300, an apparent threshold voltage V_(th) _(_) _(H) at the time when the high-level charge is given to the gate of the transistor 300 is lower than an apparent threshold voltage V_(th) _(_) _(L) at the time when the low-level charge is given to the gate of the transistor 300. Here, an apparent threshold voltage refers to the potential of the wiring 3005 that is needed to turn on the transistor 300. Thus, the potential of the wiring 3005 is set to a potential V₀ that is between V_(th) _(_) _(H) and V_(th) _(_) _(L), whereby charge supplied to the node FG can be determined. For example, in the case where the high-level charge is supplied to the node FG in writing, the transistor 300 is turned on when the potential of the wiring 3005 becomes V₀ (>V_(th) _(_) _(H). In the case where the low-level charge is supplied to the node FG in writing, the transistor 300 still remains off even when the potential of the wiring 3005 becomes V₀ (<V_(th) _(_) _(L)). Thus, the data retained in the node FG can be read by determining the potential of the wiring 3002.

By arranging the memory devices illustrated in FIG. 28 and FIG. 29 in a matrix, a memory cell array can be formed.

Note that in the case where memory cells are arrayed, it is necessary that data of a desired memory cell be read in read operation. For example, in the case of a NOR-type memory cell array, only data of a desired memory cell can be read by turning off the transistors 300 of memory cells from which data is not read. In this case, a potential at which the transistor 300 is turned off regardless of the charge supplied to the node FG, that is, a potential lower than V_(th) _(_) _(H) is supplied to the wiring 3005 connected to the memory cells from which data is not read. Alternatively, in the case of a NAND-type memory cell array, for example, only data of a desired memory cell can be read by turning on the transistors 300 of memory cells from which data is not read. In this case, a potential at which the transistor 300 is turned on regardless of the charge supplied to the node FG, that is, a potential higher than V_(th) _(_) _(L) is supplied to the wiring 3005 connected to the memory cells from which data is not read.

<Memory Device Configuration 2>

The memory devices illustrated in FIG. 28 and FIG. 29 do not necessarily include the transistor 300. Also in that case, data can be written and retained in a manner similar to that of the memory device described above.

For example, data reading in the memory device without the transistor 300 is described. When the transistor 200 is turned on, the wiring 3003 that is in a floating state and the capacitor 100 are brought into conduction, and the charge is redistributed between the wiring 3003 and the capacitor 100. As a result, the potential of the wiring 3003 is changed. The amount of change in the potential of the wiring 3003 varies depending on the potential of the one electrode of the capacitor 100 (or the charge accumulated in the capacitor 100).

For example, the potential of the wiring 3003 after the charge redistribution is (C_(B)×V_(B0)+C×V)/(C_(B)+C), where V is the potential of the one electrode of the capacitor 100, C is the capacitance of the capacitor 100, C_(B) is the capacitance component of the wiring 3003, and V_(B0) is the potential of the wiring 3003 before the charge redistribution. Thus, it can be found that, assuming that the memory cell is in either of two states in which the potential of the one electrode of the capacitor 100 is V₁ and V₀ (V₁>V₀), the potential of the wiring 3003 when the potential V₁ is retained (=(C_(B)×V_(B0)+C×V₁)/(C_(B)+C)) is higher than the potential of the wiring 3003 when the potential V₀ is retained (=(C_(B)×V_(B0)+C×V₀)/(C_(B)+C)).

Then, by comparing the potential of the wiring 3003 with a predetermined potential, data can be read.

In the case of employing the configuration, a transistor using silicon may be used for a driver circuit for driving a memory cell, and a transistor using an oxide semiconductor may be stacked as the transistor 200 over the driver circuit.

When including a transistor using an oxide semiconductor and having a small off-state current, the memory device described above can retain stored data for a long time. In other words, power consumption of the memory device can be reduced because refresh operation becomes unnecessary or the frequency of refresh operation can be extremely low. Moreover, stored data can be retained for a long time even when power is not supplied (note that a potential is preferably fixed).

In the memory device, a high voltage is not needed for data writing and deterioration of elements is unlikely to occur. Unlike in a conventional nonvolatile memory, for example, it is not necessary to inject and extract electrons into and from a floating gate; thus, a problem such as deterioration of an insulator is not caused. That is, unlike a conventional nonvolatile memory, the memory device of one embodiment of the present invention does not have a limit on the number of times data can be rewritten and the reliability thereof is drastically improved. Furthermore, data is written depending on the on/off state of the transistor, whereby high-speed operation can be achieved.

<Memory Device Structure 1>

FIG. 28 illustrates an example of the memory device of one embodiment of the present invention. The memory device includes the transistor 400, the transistor 300, the transistor 200, and the capacitor 100. The transistor 200 is provided over the transistor 300, and the capacitor 100 is provided over the transistor 300 and the transistor 200.

The transistor 300 is provided over a substrate 311 and includes a conductor 316, an insulator 314, a semiconductor region 312 that is part of the substrate 311, and low-resistance regions 318 a and 318 b functioning as source and drain regions.

The transistor 300 is either a p-channel transistor or an n-channel transistor.

It is preferable that a region of the semiconductor region 312 where a channel is formed, a region in the vicinity thereof, the low-resistance regions 318 a and 318 b functioning as source and drain regions, and the like include a semiconductor such as a silicon-based semiconductor, further preferably single crystal silicon. Alternatively, a material containing germanium (Ge), silicon germanium (SiGe), gallium arsenide (GaAs), gallium aluminum arsenide (GaAlAs), or the like may be included. Silicon whose effective mass is controlled by applying stress to the crystal lattice and thereby changing the lattice spacing may be included. Alternatively, the transistor 300 may be a high-electron-mobility transistor (HEMT) with GaAs and GaAlAs or the like.

The low-resistance regions 318 a and 318 b include an element that imparts n-type conductivity, such as arsenic or phosphorus, or an element that imparts p-type conductivity, such as boron, in addition to a semiconductor material used for the semiconductor region 312.

The conductor 316 functioning as a gate electrode can be formed using a semiconductor material such as silicon including an element that imparts n-type conductivity, such as arsenic or phosphorus, or an element that imparts p-type conductivity, such as boron, or a conductive material such as a metal material, an alloy material, or a metal oxide material.

Note that the work function of a conductor is determined by a material of the conductor, whereby the threshold voltage can be adjusted. Specifically, it is preferable to use titanium nitride, tantalum nitride, or the like as the conductor. Furthermore, in order to ensure the conductivity and embeddability of the conductor, it is preferable to use a laminated layer of metal materials such as tungsten and aluminum as the conductor. In particular, tungsten is preferable in terms of heat resistance.

Note that the transistors 300 illustrated in FIG. 28 and FIG. 29 are just examples and are not limited to the structures illustrated therein; an appropriate transistor may be used in accordance with a circuit configuration or a driving method. Note that when the memory device has the structure described in <Memory device configuration 2>, the transistor 300 is not necessarily provided.

An insulator 320, an insulator 322, an insulator 324, and an insulator 326 are stacked in this order so as to cover the transistor 300.

The insulator 320, the insulator 322, the insulator 324, and the insulator 326 can be formed using, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, or aluminum nitride.

The insulator 322 may function as a planarization film for eliminating a level difference caused by the transistor 300 or the like underlying the insulator 322. For example, the top surface of the insulator 322 may be planarized by planarization treatment using a CMP method or the like to increase the level of planarity.

The insulator 324 is preferably formed using a film with a barrier property that prevents impurities such as water or hydrogen from diffusing from the substrate 311, the transistor 300, or the like into regions where the transistor 200 and the transistor 400 are provided. A barrier property refers to a function of inhibiting the diffusion of impurities such as water or hydrogen. For example, the diffusion length of hydrogen in the film with a barrier property at 350° C. or at 400° C. is less than or equal to 50 nm per hour, preferably less than or equal to 30 nm per hour, further preferably less than or equal to 20 nm per hour.

As an example of the film having a barrier property against hydrogen, silicon nitride formed by a CVD method can be given. The diffusion of hydrogen into a semiconductor element including an oxide semiconductor, such as the transistor 200, degrades the characteristics of the semiconductor element in some cases. Therefore, a film that inhibits the diffusion of hydrogen is preferably provided between the transistors 200 and 400 and the transistor 300. Specifically, the film that inhibits the diffusion of hydrogen is a film from which hydrogen is unlikely to be released.

The released amount of hydrogen can be measured by TDS, for example. The amount of hydrogen released from the insulator 324 that is converted into hydrogen molecules per unit area of the insulator 324 is less than or equal to 2×10¹⁵ molecules/cm², preferably less than or equal to 1×10¹⁵ molecules/cm², further preferably 5×10¹⁴ molecules/cm² in TDS analysis in the range from 50° C. to 500° C., for example.

Note that the dielectric constant of the insulator 326 is preferably lower than that of the insulator 324. For example, the relative dielectric constant of the insulator 326 is preferably lower than 4, further preferably lower than 3. For example, the relative dielectric constant of the insulator 324 is preferably 0.7 times or less that of the insulator 326, further preferably 0.6 times or less that of the insulator 326. In the case where a material with a low dielectric constant is used for an interlayer film, the parasitic capacitance between wirings can be reduced.

A conductor 328, a conductor 330, and the like that are electrically connected to the capacitor 100 or the transistor 200 are embedded in the insulator 320, the insulator 322, the insulator 324, and the insulator 326. Note that the conductor 328 and the conductor 330 each function as a plug or a wiring. Note that a plurality of structures of conductors functioning as plugs or wirings are collectively denoted by the same reference numeral in some cases, as described later. Furthermore, in this specification and the like, a wiring and a plug electrically connected to the wiring may be a single component. That is, there are cases where part of a conductor functions as a wiring and part of a conductor functions as a plug.

As a material of each of plugs and wirings (e.g., the conductor 328 and the conductor 330), a conductive material such as a metal material, an alloy material, a metal nitride material, or a metal oxide material can be used in a single-layer structure or a stacked-layer structure. It is preferable to use a high-melting-point material that has both heat resistance and conductivity, such as tungsten or molybdenum, and it is particularly preferable to use tungsten. Alternatively, a low-resistance conductive material such as aluminum or copper is preferably used. The use of a low-resistance conductive material can reduce wiring resistance.

A wiring layer may be provided over the insulator 326 and the conductor 330. For example, in FIG. 28, an insulator 350, an insulator 352, and an insulator 354 are stacked in this order. Furthermore, a conductor 356 is formed in the insulator 350, the insulator 352, and the insulator 354. The conductor 356 functions as a plug or a wiring. Note that the conductor 356 can be formed using a material similar to that for the conductor 328 and the conductor 330.

Note that for example, the insulator 350 is preferably formed using an insulator having a barrier property against hydrogen, like the insulator 324. Furthermore, the conductor 356 preferably includes a conductor having a barrier property against hydrogen. The conductor having a barrier property against hydrogen is formed particularly in an opening portion of the insulator 350 having a barrier property against hydrogen. In such a structure, the transistor 300 can be separated from the transistors 200 and 400 by a barrier layer, so that the diffusion of hydrogen from the transistor 300 into the transistors 200 and 400 can be inhibited.

Note that as the conductor having a barrier property against hydrogen, tantalum nitride is preferably used, for example. By stacking tantalum nitride and tungsten, which has high conductivity, the diffusion of hydrogen from the transistor 300 can be inhibited while the conductivity of a wiring is ensured. In this case, a tantalum nitride layer having a barrier property against hydrogen is preferably in contact with the insulator 350 having a barrier property against hydrogen.

An insulator 358, an insulator 210, the insulator 212, the insulator 214, and the insulator 216 are stacked in this order over the insulator 354. A material having a barrier property against oxygen or hydrogen is preferably used for any of the insulator 358, the insulator 210, the insulator 212, the insulator 214, and the insulator 216.

The insulator 358, the insulator 212, and the insulator 214 are each preferably formed using, for example, a film having a barrier property that prevents impurities such as water or hydrogen from diffusing from the substrate 311, a region where the transistor 300 is provided, or the like into the regions where the transistor 200 and the transistor 400 are provided. Therefore, the insulator 358, the insulator 212, and the insulator 214 can be formed using a material similar to that for the insulator 324.

As an example of the film having a barrier property against hydrogen, silicon nitride formed by a CVD method can be given. The diffusion of hydrogen into a semiconductor element including an oxide semiconductor, such as the transistor 200, degrades the characteristics of the semiconductor element in some cases. Therefore, a film that inhibits the diffusion of hydrogen is preferably provided between the transistors 200 and 400 and the transistor 300. Specifically, the film that inhibits the diffusion of hydrogen is a film from which hydrogen is unlikely to be released.

As the film having a barrier property against hydrogen, for example, as each of the insulator 212 and the insulator 214, a metal oxide such as aluminum oxide, hafnium oxide, or tantalum oxide is preferably used.

In particular, aluminum oxide has an excellent blocking effect that prevents the passage of oxygen and impurities such as water or hydrogen that cause a change in electrical characteristics of the transistor. Accordingly, the use of aluminum oxide can prevent entry of impurities such as water or hydrogen into the transistors 200 and 400 in and after a manufacturing process of the transistor. In addition, release of oxygen from the oxide in the transistor 200 can be inhibited. Therefore, aluminum oxide is suitably used as a protective film for the transistors 200 and 400.

For example, the insulator 210 and the insulator 216 can be formed using a material similar to that for the insulator 320. The use of a material with a relatively low dielectric constant for the insulators can reduce the parasitic capacitance between wirings. For example, a silicon oxide film, a silicon oxynitride film, or the like can be used as the insulator 216.

A conductor 218, conductors included in the transistor 200 and the transistor 400 (the conductor 205, the conductor 405, the conductor 403, and the conductor 407), and the like are embedded in the insulator 358, the insulator 210, the insulator 212, the insulator 214, and the insulator 216. Note that the conductor 218 functions as a plug or a wiring that is electrically connected to the capacitor 100 or the transistor 300. The conductor 218 can be formed using a material similar to that for the conductor 328 and the conductor 330.

In particular, the conductor 218 in a region in contact with the insulator 358, the insulator 212, and the insulator 214 is preferably a conductor having a barrier property against oxygen, hydrogen, and water. In such a structure, the transistor 300 and the transistor 200 can be completely separated by the layer having a barrier property against oxygen, hydrogen, and water, so that the diffusion of hydrogen from the transistor 300 into the transistors 200 and 400 can be inhibited.

The transistor 200 and the transistor 400 are provided over the insulator 216. Note that as the transistors 200 and 400, the transistors 200 and 400 described in Embodiment 1 are preferably used.

An insulator 110 is provided over the transistor 200 and the transistor 400. The insulator 110 can be formed using a material similar to that for the insulator 320. The use of a material with a relatively low dielectric constant for the insulator can reduce the parasitic capacitance between wirings. For example, a silicon oxide film or a silicon oxynitride film can be used as the insulator 110.

A conductor 285 and the like are embedded in the insulator 220, the insulator 222, the insulator 224, the insulator 272, the insulator 274, and the insulator 110.

Note that the conductor 285 functions as a plug or a wiring that is electrically connected to the capacitor 100, the transistor 200, or the transistor 300. The conductor 285 can be formed using a material similar to that for the conductor 328 and the conductor 330.

For example, in the case where the conductor 285 is formed to have a stacked-layer structure, it preferably includes a conductor that is unlikely to be oxidized (that has high oxidation resistance). It is particularly preferable that a conductor having high oxidation resistance be provided so as to be in contact with the insulator 224 including an excess oxygen region. Such a structure permits inhibition of absorption of excess oxygen from the insulator 224 by the conductor 285. Furthermore, the conductor 285 preferably includes a conductor having a barrier property against hydrogen. In particular, when a conductor having a barrier property against impurities such as water or hydrogen is provided in contact with the insulator 224 including an excess oxygen region, the diffusion of impurities in the conductor 285 and part of the conductor 285 and the diffusion of impurities from the outside through the conductor 285 can be inhibited.

A conductor 287, the capacitor 100, and the like are provided over the insulator 110 and the conductor 285. The capacitor 100 includes a conductor 112, an insulator 130, an insulator 132, an insulator 134, and a conductor 116. The conductor 112 and the conductor 116 function as the electrodes of the capacitor 100, and the insulator 130, the insulator 132, and the insulator 134 function as dielectrics of the capacitor 100.

The conductor 287 functions as a plug or a wiring that is electrically connected to the capacitor 100, the transistor 200, or the transistor 300. The conductor 112 functions as the one electrode of the capacitor 100. The conductor 287 and the conductor 112 can be formed at the same time.

For the conductor 287 and the conductor 112, a metal film containing an element selected from molybdenum, titanium, tantalum, tungsten, aluminum, copper, chromium, neodymium, and scandium; a metal nitride film containing any of the above elements as its component (e.g., a tantalum nitride film, a titanium nitride film, a molybdenum nitride film, or a tungsten nitride film); or the like can be used. Alternatively, a conductive material such as indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, or indium tin oxide to which silicon oxide is added can be used.

The insulator 130, the insulator 132, and the insulator 134 can each be formed to have a single-layer structure or a stacked-layer structure using, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, hafnium oxide, hafnium oxynitride, hafnium nitride oxide, or hafnium nitride.

For example, the use of a high dielectric constant (high-k) material, such as aluminum oxide, for the insulator 132 can increase the capacitance per unit area of the capacitor 100. Furthermore, a material having high dielectric strength, such as silicon oxynitride, is preferably used for the insulator 130 and the insulator 134. When a ferroelectric is located between insulators with high dielectric strength, electrostatic breakdown of the capacitor 100 can be suppressed and the capacitor can have large capacitance.

The conductor 116 is provided so as to cover the top and side surfaces of the conductor 112 with the insulator 130, the insulator 132, and the insulator 134 therebetween. In the structure where the side surfaces of the conductor 112 are wrapped by the conductor 116 with the insulators therebetween, capacitance is also formed on the side surfaces of the conductor 112, resulting in an increase in the capacitance per unit projected area of the capacitor. Thus, the memory device can be reduced in area, highly integrated, and miniaturized.

Note that the conductor 116 can be formed using a conductive material such as a metal material, an alloy material, or a metal oxide material. It is preferable to use a high-melting-point material that has both heat resistance and conductivity, such as tungsten or molybdenum, and it is particularly preferable to use tungsten. In the case where the conductor 116 is formed concurrently with another component such as a conductor, Cu, Al, or the like, which is a low-resistance metal material, may be used.

An insulator 150 is provided over the conductor 116 and the insulator 134. The insulator 150 can be formed using a material similar to that for the insulator 320. The insulator 150 may function as a planarization film that covers roughness due to underlying layers.

The above is the description of the structure example. With the use of the structure, a change in electrical characteristics can be suppressed and reliability can be improved in a memory device including a transistor including an oxide semiconductor. Alternatively, a transistor including an oxide semiconductor with a large on-state current can be provided. A transistor including an oxide semiconductor with a small off-state current can be provided. Alternatively, a memory device with low power consumption can be provided.

Modification Example 1

FIG. 29 illustrates a modification example of the memory device. FIG. 29 is different from FIG. 28 in the structure of the transistor 300, the shapes of the insulators 272 and 274, and the like.

In the transistor 300 illustrated in FIG. 29, the semiconductor region 312 (part of the substrate 311) in which a channel is formed includes a protruding portion. Furthermore, the conductor 316 is provided so as to cover the top and side surfaces of the semiconductor region 312 with the insulator 314 therebetween. Note that the conductor 316 may be formed using a material for adjusting the work function. The transistor 300 is also referred to as a FIN transistor because it utilizes a protruding portion of the semiconductor substrate. An insulator functioning as a mask for forming the protruding portion may be provided in contact with the top surface of the protruding portion. Although the case where the protruding portion is formed by processing part of the semiconductor substrate is described here, a semiconductor film having a protruding portion may be formed by processing an SOI substrate.

The use of a combination of the transistor 300 and the transistor 200 that have the structure enables a reduction in area, high integration, and miniaturization.

Moreover, as illustrated in FIG. 29, the insulator 220 and the insulator 222 are not necessarily provided. Such a structure can increase the productivity.

Furthermore, as illustrated in FIG. 29, the bottom surface of the insulator 272 and the top surface of the insulator 214 may be in contact with each other in openings formed in the insulator 216 and the insulator 224.

The above is the description of the modification example. With the use of the structure, a change in electrical characteristics can be suppressed and reliability can be improved in a memory device including a transistor including an oxide semiconductor. Furthermore, a transistor including an oxide semiconductor with a large on-state current can be provided. Furthermore, a transistor including an oxide semiconductor with a small off-state current can be provided. Furthermore, a memory device with low power consumption can be provided.

Modification Example 2

FIG. 30 illustrates a modification example of this embodiment. FIG. 30 is a cross-sectional view that shows part of a row in which the memory devices each of which is illustrated in FIG. 28 are arranged in a matrix.

In FIG. 30, the memory device that includes the transistor 300, the transistor 200, and the capacitor 100 and the memory device that includes a transistor 301, a transistor 201, and a capacitor 101 are arranged in the same row.

As illustrated in FIG. 30, a plurality of transistors (the transistors 200 and 201 in the figure) and the insulator 224 including an oxygen-excess region may be enclosed with a stacked-layer structure of the insulators 212 and 214 and a stacked-layer structure of the insulators 282 and 284. At that time, a structure in which the insulators 212 and 214 and the insulators 282 and 284 are stacked is preferably formed between the transistor 200 or 201 and a through electrode that connects the transistor 300 or 301 and the capacitor 100 or 101.

Note that an opening formed in the insulators 216, 220, 222, 224, 272, 274, and 280 can be formed at the same time as the opening 480 described in Embodiment 1.

Thus, oxygen released from the insulator 224 and the transistors 200 and 201 can be inhibited from diffusing into the layer where the capacitors 100 and 101 are formed or the layer where the transistor 300 and 301 are formed. Furthermore, impurities such as water or hydrogen can be inhibited from diffusing from a layer over the insulator 282 and a layer under the insulator 214 into the transistor 200 or 201.

That is, oxygen can be efficiently supplied from the excess-oxygen region of the insulator 224 to oxide where channels are formed in the transistors 200 and 201, so that oxygen vacancies can be reduced. Moreover, oxygen vacancies can be prevented from being formed by impurities in the oxide where a channel is formed in the transistor 200. Thus, the oxide where channels are formed in the transistors 200 and 201 can be an oxide semiconductor with a low density of defect states and stable characteristics. That is, a change in electrical characteristics of the transistors 200 and 201 can be prevented and the reliability can be improved.

At least part of this embodiment can be implemented in combination with any of the other embodiments described in this specification as appropriate.

Example 1

In this example, Sample 1A in which an In—Ga—Zn oxide film (hereinafter, referred to as an IGZO film), an In—Sn—Si oxide film (hereinafter, referred to as an ITSO film), and a tantalum nitride film are stacked over a silicon oxide film and Sample 1B in which the ITSO film of Sample 1A is replaced with an In—Zn oxide film (hereinafter, referred to as an indium zinc oxide film) were fabricated and then subjected to substrate side depth profile SIMS (SSDP-SIMS) analysis to evaluate the concentration of hydrogen. The results of the evaluation are described.

A method for fabricating Samples 1A and 1B used for the SSDP-SIMS analysis is described below.

First, in each of Samples 1A and 1B, by thermal oxidation of a silicon wafer, a 100-nm-thick silicon oxide film was formed on a surface of the silicon wafer. The thermal oxidation was performed at a substrate temperature of 950° C. in an oxygen atmosphere containing HCl at 3 volume %.

Next, in each of Samples 1A and 1B, a 100-nm-thick IGZO film was formed by a DC sputtering method. Note that the atomic ratio of a target used for forming the IGZO film was In:Ga:Zn=4:2:4.1. As the deposition gases, an argon gas at 40 sccm and an oxygen gas at 5 sccm were used. The deposition pressure was 0.7 Pa (measured by Miniature Gauge MG-2 manufactured by CANON ANELVA CORPORATION). The deposition power was 500 W. The substrate temperature was 130° C. The distance between the target and the substrate was 60 mm.

Then, in Sample 1A, a 100-nm-thick ITSO film was formed by a DC sputtering method. Note that the composition of a target used for forming the ITSO film was In₂O₃:SnO₂:SiO₂=85:10:5 [wt %]. As the deposition gases, an argon gas at 50 sccm and an oxygen gas at 3 sccm were used. The deposition pressure was 0.4 Pa. The deposition power was 500 W. The substrate temperature was room temperature. The distance between the target and the substrate was 170 mm.

In Sample 1B, a 100-nm-thick indium zinc oxide film was formed by a DC sputtering method. Note that the composition of a target used for forming the indium zinc oxide film was In₂O₃:ZnO=89.7:10.7 [wt %]. As the deposition gases, an argon gas at 50 sccm and an oxygen gas at 3 sccm were used. The deposition pressure was 0.4 Pa. The deposition power was 500 W. The substrate temperature was room temperature. The distance between the target and the substrate was 170 mm.

Next, in each of Samples 1A and 1B, a 30-nm-thick tantalum nitride film was formed by a DC sputtering method. Note that a Ta target was used for forming the tantalum nitride film. As the deposition gases, an argon gas at 50 sccm and an nitrogen gas at 10 sccm were used. The deposition pressure was 0.6 Pa. The deposition power was 1000 W. The substrate temperature was room temperature. The distance between the target and the substrate was 60 mm.

FIGS. 31A and 31B show the results of hydrogen detected in the SSDP-SIMS analysis performed on Samples 1A and 1B fabricated in the above manner. FIG. 31A shows the concentration of hydrogen in Sample 1A, and FIG. 31B shows the concentration of hydrogen in Sample 1B. In FIGS. 31A and 31B, the horizontal axis shows a depth [nm], and the vertical axis shows the concentration of hydrogen [atoms/cm³]. The concentration of hydrogen at the long dashed line near 1.0×10¹⁸ atoms/cm³ shows a background level of the SIMS analysis device. The SSDP-SIMS analysis of Samples 1A and 1B was performed while the samples were dug from the silicon wafer side. In the SSDP-SIMS analysis of Samples 1A and 1B, the IGZO film was quantified, and the concentration of hydrogen in the IGZO film was converted. Note that the SIMS analysis was performed by using an ADEPT-1010 quadrupole mass spectrometry instrument manufactured by ULVAC-PHI, Inc.

As shown in FIG. 31A, the concentration of hydrogen in the IGZO film of Sample 1A is as low as the background level. Similarly, as shown in FIG. 31B, the concentration of hydrogen in the IGZO film of Sample 1B is also as low as the background level.

The above shows that hydrogen in the IGZO film is gettered by the ITSO film or the indium zinc oxide film by providing the ITSO film or the indium zinc oxide film so as to be in contact with the IGZO film.

In this example, the period from the formation of Samples 1A and 1B to the SSDP-SIMS analysis was six days. During the period, hydrogen in the IGZO film and in the vicinity of the IGZO film was gettered by the ITSO film or the indium zinc oxide film and was prevented from entering the IGZO film. Thus, long-term reliability of the completed semiconductor device can be improved by providing the ITSO film or the indium zinc oxide film so as to be in contact with the IGZO film.

This application is based on Japanese Patent Application serial No. 2016-086232 filed with Japan Patent Office on Apr. 22, 2016, the entire contents of which are hereby incorporated by reference. 

What is claimed is:
 1. A semiconductor device comprising: a first barrier insulating film; a first gate electrode over the first barrier insulating film; a first gate insulating film over the first gate electrode; an oxide semiconductor film over the first gate insulating film; a source electrode and a drain electrode that are apart from each other over the oxide semiconductor film; a second gate insulating film over the oxide semiconductor film, the source electrode, and the drain electrode; a second gate electrode which is over the second gate insulating film and at least part of which overlaps with a region between the source electrode and the drain electrode; a second barrier insulating film that covers the oxide semiconductor film, the source electrode, the drain electrode, the second gate electrode, and the second gate insulating film, and is in contact with side surfaces of the oxide semiconductor film, the source electrode, and the drain electrode and a top surface of the first gate insulating film; and a third barrier insulating film over the second barrier insulating film, wherein the first barrier insulating film, the second barrier insulating film, and the third barrier insulating film are less likely to transmit hydrogen, water, and oxygen than the first gate insulating film and the second gate insulating film, wherein the third barrier insulating film has a smaller thickness than the second barrier insulating film, wherein the source electrode comprises a first conductive layer in contact with the oxide semiconductor film and a second conductive layer over the first conductive layer, wherein the drain electrode comprises a third conductive layer in contact with the oxide semiconductor film and a fourth conductive layer over the third conductive layer, wherein each of the first conductive layer and the third conductive layer comprise a conductive oxide film, and wherein the conductive oxide film has a larger number of oxygen vacancies than the oxide semiconductor film.
 2. The semiconductor device according to claim 1, further comprising: a first insulator in contact with a top surface of the second conductive layer; and a second insulator in contact with a top surface of the fourth conductive layer, wherein the first insulator and the second insulator are less likely to transmit oxygen than the first gate insulating film and the second gate insulating film.
 3. The semiconductor device according to claim 1, wherein the conductive oxide film comprises indium.
 4. The semiconductor device according to claim 1, wherein each of the first barrier insulating film, the second barrier insulating film, and the third barrier insulating film comprises oxygen and aluminum.
 5. A semiconductor device comprising: a first insulator; a second insulator over the first insulator; a first conductor over the second insulator; a third insulator over the first conductor; a first oxide over the third insulator; a second oxide over the first oxide; a first conductive oxide and a second conductive oxide that are apart from each other over the second oxide; a second conductor over the first conductive oxide; a third conductor over the second conductive oxide; a third oxide that is over the second oxide, the first conductive oxide, the second conductive oxide, the second conductor, and the third conductor and is in contact with a top surface and a side surface of the second oxide, a side surface of the first oxide, and a top surface of the third insulator; a fourth insulator over the third oxide; a fourth conductor positioned over the fourth insulator so that at least part of the fourth conductor overlaps with a region between the second conductor and the third conductor; a fifth insulator provided in contact with a side surface of the first conductive oxide, a side surface of the second conductive oxide, the side surface of the second oxide, and the top surface of the third insulator so as to cover the first oxide, the second oxide, the third oxide, the first conductive oxide, the second conductive oxide, the second conductor, the third conductor, the fourth conductor, and the fourth insulator; and a sixth insulator over the fifth insulator, wherein the first, second, fifth, and sixth insulators are less likely to transmit hydrogen, water, and oxygen than the third and fourth insulators, wherein the first insulator has a smaller thickness than the second insulator, and the sixth insulator has a smaller thickness than the fifth insulator, and wherein the first conductive oxide and the second conductive oxide each have a larger number of oxygen vacancies than the second oxide.
 6. The semiconductor device according to claim 5, further comprising: a seventh insulator in contact with a top surface of the fourth conductor, wherein the seventh insulator is less likely to transmit oxygen than the third and fourth insulators.
 7. The semiconductor device according to claim 6, further comprising: an eighth insulator in contact with a top surface of the second conductor; and a ninth insulator in contact with a top surface of the third conductor, wherein the eighth insulator and the ninth insulator are less likely to transmit oxygen than the third insulator and the fourth insulator.
 8. The semiconductor device according to claim 7, wherein the eighth insulator and the ninth insulator each comprise oxygen and aluminum.
 9. The semiconductor device according to claim 5, further comprising: a tenth insulator over the sixth insulator; an eleventh insulator over the tenth insulator; and a twelfth insulator over the eleventh insulator, wherein the third insulator, the fifth insulator, the sixth insulator, and the tenth insulator have an opening reaching the second insulator and the eleventh insulator is in contact with a top surface of the second insulator through the opening, wherein the opening is provided so as to surround an external side of the second oxide, wherein the eleventh insulator and the twelfth insulator are less likely to transmit hydrogen, water, and oxygen than the tenth insulator, and wherein the twelfth insulator has a smaller thickness than the eleventh insulator.
 10. The semiconductor device according to claim 5, wherein the first conductive oxide and the second conductive oxide each comprise indium.
 11. The semiconductor device according to claim 10, wherein a density of indium comprised in the first conductive oxide and the second conductive oxide is higher than a density of indium comprised in the second oxide.
 12. The semiconductor device according to claim 10, wherein the first conductive oxide and the second conductive oxide each comprise zinc.
 13. The semiconductor device according to claim 10, wherein the first conductive oxide and the second conductive oxide each comprise tin and silicon.
 14. The semiconductor device according to claim 5, wherein the first oxide, the second oxide, and the third oxide comprise In, M that is Al, Ga, Y, or Sn, and Zn.
 15. The semiconductor device according to claim 5, wherein the third insulator and the fourth insulator each comprise oxygen and silicon.
 16. The semiconductor device according to claim 5, wherein the first insulator, the second insulator, the fifth insulator, and the sixth insulator comprise oxygen and aluminum.
 17. A semiconductor device comprising: a first barrier insulating film; a first gate electrode over the first barrier insulating film; a first gate insulating film over the first gate electrode; an oxide semiconductor film over the first gate insulating film; a source electrode and a drain electrode that are apart from each other over the oxide semiconductor film; a second gate insulating film over the oxide semiconductor film, the source electrode, and the drain electrode; a second gate electrode which is over the second gate insulating film and at least part of which overlaps with a region between the source electrode and the drain electrode; and a second barrier insulating film that covers the oxide semiconductor film, the source electrode, the drain electrode, the second gate electrode, and the second gate insulating film, and is in contact with side surfaces of the oxide semiconductor film, the source electrode, and the drain electrode and a top surface of the first gate insulating film; wherein each of the first barrier insulating film and the second barrier insulating film comprises oxygen and aluminum, wherein the source electrode comprises a first conductive layer in contact with the oxide semiconductor film and a second conductive layer over the first conductive layer, wherein the drain electrode comprises a third conductive layer in contact with the oxide semiconductor film and a fourth conductive layer over the third conductive layer, and wherein each of the first conductive layer and the third conductive layer comprise a conductive oxide film.
 18. The semiconductor device according to claim 17, wherein the conductive oxide film has a larger number of oxygen vacancies than the oxide semiconductor film.
 19. The semiconductor device according to claim 17, further comprising: a first insulator in contact with a top surface of the second conductive layer; and a second insulator in contact with a top surface of the fourth conductive layer, wherein the first insulator and the second insulator are less likely to transmit oxygen than the first gate insulating film and the second gate insulating film.
 20. The semiconductor device according to claim 17, wherein the conductive oxide film comprises indium.
 21. The semiconductor device according to claim 17, wherein the first barrier insulating film and the second barrier insulating film are less likely to transmit hydrogen, water, and oxygen than the first gate insulating film and the second gate insulating film. 